IDiyas

For the Inventor, By the Inventor

Berkeley, CA, United States of America

Philip Chong

USPTO Granted Patents = 11

Average Co-Inventor Count = 3.2

ph-index = 8

Forward Citations = 132(Granted Patents)


Company Filing History:

goldMedal8 out of 2,542 
 
Cadence Design Systems, Inc.
 patents
silverMedal2 out of 2,485 
 
Synopsys, Inc.
 patents
bronzeMedal1 out of 832,680 
Other
 patents

Years Active: 2009-2017

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11 patents (USPTO):
1. 9836390 - Static analysis of computer code to determine impact of change to a code component upon a dependent code component (2017-12-05),
2. 9032376 - Static analysis of computer code to determine impact of change to a code component upon a dependent code component (2015-05-12),
3. 8589845 - Optimizing integrated circuit design through use of sequential timing information (2013-11-19),
4. 8572540 - Method and system for approximate placement in electronic designs (2013-10-29),
5. 8307316 - Reducing critical cycle delay in an integrated circuit design through use of sequential slack (2012-11-06),
6. 8028263 - Method, system, and computer program product for implementing incremental placement in electronics design (2011-09-27),
7. 7966595 - Method and system for approximate placement in electronic designs (2011-06-21),
8. 7913210 - Reducing critical cycle delay in an integrated circuit design through use of sequential slack (2011-03-22),
9. 7743354 - Optimizing integrated circuit design through use of sequential timing information (2010-06-22),
10. 7739644 - Methods, systems, and computer program products for grid-morphing techniques in placement, floorplanning, and legalization (2010-06-15),
11. 7624364 - Data path and placement optimization in an integrated circuit through use of sequential timing information (2009-11-24),
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