The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 27, 2011

Filed:

Aug. 08, 2008
Applicants:

Philip Chong, Berkeley, CA (US);

Christian Szegedy, Albany, CA (US);

Inventors:

Philip Chong, Berkeley, CA (US);

Christian Szegedy, Albany, CA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Disclosed are a method, system, and computer program product for implementing incremental placement for an electronic design while predicting and minimizing a perturbation impact arising from incremental placement of electronic components. In some embodiments, an initial placement of an electronic design is identified, an abstract flow is computed, target locations of various electronic components to be placed are identified, a relative ordering of electronic components is determined, and the placement is then legalized. Furthermore, in various embodiments, the method, system, or computer program product starts with an initial placement of an electronic design and derives a legal placement by using an incremental placement technique while minimizing the perturbation impact or an total quadratic movement of instances. In some embodiments, an augmented or incremental clumping technique based data structure is utilized for rapid and substantially exact perturbation prediction of effects of local incremental placement operations.


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