Cadence Design Systems, Inc.

Synopsys, Inc.

Other

Philip Chong

Andreas Kuehlmann

Christoph Albrecht

Ellen Sentovich

Roberto Passerone

Christian Szegedy

Marat Boshernitsan

Scott McPeak

Tobias Welp

A method is provided to evaluate impact of a change to code of a depended upon component of a system stored in a computer readable storage device, upon a dependent component of the system, the method comprising: identifying a dependency relationship between a first component stored in a computer readable storage device and a second component stored in the computer readable storage device; in response to a determination that the second component depends upon the first component, configuring a computer system to obtain a first property evaluation corresponding to the first component; and in response to obtaining the first property evaluation corresponding to the first component, configuring the computer system to associate the first property evaluation with the second component, and obtain a second property evaluation corresponding to the second component, wherein the second component is associated with the first property evaluation.

Static analysis of computer code to determine impact of change to a code component upon a dependent code component

A method is provided to evaluate impact of a change in code of a depended upon component of a system stored in a computer readable storage device, upon a dependent component of the system, the method comprising: identifying a dependency relationship between a first component stored in a computer readable storage device and a second component stored in the computer readable storage device; in response to a determination that the second component depends upon the first component, configuring a computer system to obtain a first property evaluation corresponding to the first component; and in response to obtaining the first property evaluation corresponding to the first component, configuring the computer system to associate the first property evaluation with the second component, and obtain a second property evaluation corresponding to the second component, wherein the second component is associated with the first property evaluation.

A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to ascertain sequential optimization based design flexibility throughout multiple stages of a design flow.

Optimizing integrated circuit design through use of sequential timing information

Disclosed are method, system, and computer program product for a method and system for a fast and stable placement/floorplanning method that gives consistent and good quality results. Various embodiments of the present invention provide a method and system for approximate placement of various standard cells, macro-blocks, and I/O pads for the design of integrated circuits by approximating the final shapes of the objects of interest by one or more probability distribution functions over the areas for the objects of interest with improved runtime and very good stability. These probability distributions are gradually localized to final shapes satisfying the placement constraints and optimizing an objective function.

Method and system for approximate placement in electronic designs

Reducing critical cycle delay in an integrated circuit design through use of sequential slack

Disclosed are a method, system, and computer program product for implementing incremental placement for an electronic design while predicting and minimizing a perturbation impact arising from incremental placement of electronic components. In some embodiments, an initial placement of an electronic design is identified, an abstract flow is computed, target locations of various electronic components to be placed are identified, a relative ordering of electronic components is determined, and the placement is then legalized. Furthermore, in various embodiments, the method, system, or computer program product starts with an initial placement of an electronic design and derives a legal placement by using an incremental placement technique while minimizing the perturbation impact or an total quadratic movement of instances. In some embodiments, an augmented or incremental clumping technique based data structure is utilized for rapid and substantially exact perturbation prediction of effects of local incremental placement operations.

Method, system, and computer program product for implementing incremental placement in electronics design

Disclosed are methods, systems, and computer program products for performing grid morphing technique for computing a spreading of objects over an area such that the final locations of the objects are distributed over the area and such that the final locations of the objects are minimally perturbed from their initial starting locations and the density of objects meets certain constraints. The minimization of perturbation, or stability, of the approaches disclosed, is the key feature which is the principal benefit of the techniques disclosed. The methods described herein may be used as part of a tool for placement or floorplanning of logic gates or larger macroblocks for the design of an integrated circuit.

Growing community of inventors

Berkeley, CA, United States of America

Philip Chong