The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 06, 2012
Filed:
Mar. 21, 2011
Christoph Albrecht, Berkeley, CA (US);
Philip Chong, Berkeley, CA (US);
Andreas Kuehlmann, Berkeley, CA (US);
Ellen Sentovich, Oakland, CA (US);
Roberto Passerone, Trento, IT;
Christoph Albrecht, Berkeley, CA (US);
Philip Chong, Berkeley, CA (US);
Andreas Kuehlmann, Berkeley, CA (US);
Ellen Sentovich, Oakland, CA (US);
Roberto Passerone, Trento, IT;
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to ascertain sequential optimization based design flexibility throughout multiple stages of a design flow.