IDiyas

For the Inventor, By the Inventor

Trento, Italy

Roberto Passerone

USPTO Granted Patents = 6

Average Co-Inventor Count = 4.5

ph-index = 6

Forward Citations = 97(Granted Patents)


Location History:

  • Berkeley, CA (US) (2006)
  • Trento, IT (2009 - 2013)

Company Filing History:

goldMedal5 out of 2,542 
 
Cadence Design Systems, Inc.
 patents
silverMedal1 out of 832,680 
Other
 patents

Years Active: 2006-2013

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6 patents (USPTO):
1. 8589845 - Optimizing integrated circuit design through use of sequential timing information (2013-11-19),
2. 8307316 - Reducing critical cycle delay in an integrated circuit design through use of sequential slack (2012-11-06),
3. 7913210 - Reducing critical cycle delay in an integrated circuit design through use of sequential slack (2011-03-22),
4. 7743354 - Optimizing integrated circuit design through use of sequential timing information (2010-06-22),
5. 7624364 - Data path and placement optimization in an integrated circuit through use of sequential timing information (2009-11-24),
6. 7136947 - System and method for automatically synthesizing interfaces between incompatible protocols (2006-11-14),
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