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Peter A Beerel

USPTO Granted Patents = 17 (Patent Applications = 1)

Average Co-Inventor Count = 3.5

ph-index = 8

Forward Citations = 395(Granted Patents)

Location History:

Long Beach, CA (US) (1999)
Westminster, CA (US) (2003)
Westminister, CA (US) (2004 - 2007)
Encino, CA (US) (2004 - 2018)

Company Filing History:

9 out of 1,630

University of Southern California

patents

7 out of 20

Fulcrum Microsystems, Inc.

where one patent can have more than one assignee

Years Active: 1999-2018

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17 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 9875327 - Timing violation resilient asynchronous template (2018-01-23),

2. 9558309 - Timing violation resilient asynchronous template (2017-01-31),

3. 8972915 - Static timing analysis of template-based asynchronous circuits (2015-03-03),

4. 8495543 - Multi-level domino, bundled data, and mixed templates (2013-07-23),

5. 8448105 - Clustering and fanout optimizations of asynchronous circuits (2013-05-21),

6. 8086975 - Power aware asynchronous circuits (2011-12-27),

7. 8051396 - Logic synthesis of multi-level domino asynchronous pipelines (2011-11-01),

8. 7584449 - Logic synthesis of multi-level domino asynchronous pipelines (2009-09-01),

9. 7197691 - Reduced-latency soft-in/soft-out module (2007-03-27),

10. 6854096 - Optimization of cell subtypes in a hierarchical design flow (2005-02-08),

11. 6785875 - Methods and apparatus for facilitating physical synthesis of an integrated circuit design (2004-08-31),

12. 6690752 - Sequential decoder for decoding of convolutional codes (2004-02-10),

13. 6526551 - Formal verification of a logic design through implicit enumeration of strongly connected components (2003-02-25),

14. 5978899 - Apparatus and method for parallel processing and self-timed serial (1999-11-02),

15. 5948096 - Apparatus and method for self-timed marking of variable length (1999-09-07),

Title: Inventor Spotlight: Peter A. Beerel

Introduction

Peter A. Beerel, an accomplished inventor based in Encino, California, has made significant contributions to the field of asynchronous circuit design. With a remarkable portfolio of 13 patents, Beerel’s work focuses on enhancing the reliability and performance of electronic systems.

Latest Patents

Among his latest innovations is the "Timing Violation Resilient Asynchronous Template." This invention involves an asynchronous circuit that features a single-rail logic datapath, integrated with error-detecting latches and a controller. The system is designed to work in harmony with delay lines to ensure that the output of the error-detecting latches is validated before the latches communicate whether an error has occurred. This innovative approach aims to improve the resilience and efficiency of asynchronous circuits, making them more reliable in various applications.

Career Highlights

Beerel has had an impressive career, marked by pivotal roles at prominent organizations such as the University of Southern California and Fulcrum Microsystems, Inc. His experiences at these institutions have not only honed his expertise but also positioned him as a valuable contributor in the field of electronics and circuit design.

Collaborations

Throughout his career, Peter has collaborated with notable individuals such as Andrew M. Lines and Georgios Dimou. These collaborations have furthered his innovations and allowed him to bring some of his most significant ideas to fruition.

Conclusion

Peter A. Beerel is a distinguished inventor whose work in asynchronous circuit design continues to shape the future of electronic systems. His 13 patents showcase a deep commitment to innovation and excellence, making him a prominent figure in his field. As technology advances, contributions like Beerel’s play an essential role in driving the industry forward.

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