The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 31, 2004

Filed:

Jan. 28, 2003
Applicant:
Inventors:

Peter Beerel, Encino, CA (US);

Andrew Lines, Calabasas, CA (US);

Qing Wu, Irvine, CA (US);

Assignee:

Fulcrum Microsystems, Inc., Calabasas Hills, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/45 ; G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 9/45 ; G06F 1/750 ;
Abstract

Methods and apparatus are described for facilitating physical synthesis of an integrated circuit design. A set of paths between observable nodes in a netlist representing the circuit design is generated. Each path corresponds to a sequence of signal transitions. Transistors represented in the netlist are sized to attempt to meet a delay constraint for each path. The delay constraint corresponds to a unit delay times the number of signal transitions in the corresponding path. A plurality of individual delays of different durations are allocated among the transitions for at least one of the paths to meet the delay constraint. At least one of the individual delays exceeds the unit delay.


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