The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 25, 2003
Filed:
Jun. 28, 2001
Aiguo Xie, Alhambra, CA (US);
Peter A. Beerel, Westminster, CA (US);
University of Southern California, Los Angeles, CA (US);
Abstract
Formal verification of a logic design through implicit enumeration of strongly connected components. The invention provides for efficient, cost-effective formal verification of logical circuits and systems using a method that is much less computationally expensive than other known methods. A digraph is recursively decomposed using reachability analysis. Non-trivial, strongly connected components derived through the use of the invention can be compared to expected behavior of a circuit or system. Alternatively, the invention can be applied to detect so-called “bad cycles” which are encountered in many formal verification problems.