University of Southern California

Fulcrum Microsystems, Inc.

Intel Corporation

Peter A Beerel

Andrew M Lines

Shai Rotem

Ran Ginosar

Rakefet Kol

Kenneth Scott Stevens

Christopher John Myers

Kenneth Yi Yun

Georgios Dimou

Keith Michael Chugg

Michael I Davies

Melvin A Breuer

Phunsak Thiennviboon

Benmao Cheng

Dylan Hand

Sushil Kumar Singh

Recep O Ozdag

Sunan Tugsinavisut

Ken Shiring

Aiguo Xie

Arash Saifhashemi

Frederik Eaton

Mallika Prakash

Qing Wu

An asynchronous circuit may include a single-rail logic datapath; one or more error-detecting latches; a controller that controls the error-detecting latches; and delay lines. The controller and the delay lines may cooperate to communicate with one or more other controllers that the output of the controlled error-detecting latches may be valid prior to when the error-detecting latches indicate whether or not an error occurred.

Timing violation resilient asynchronous template

Effective timing and power characterization flows are described for asynchronous circuits. Verification can be provided for both relative-timing constraints as well as performance (e.g., throughput) targets using commercially-standard STA tools. Fully-automated scripts are developed that verify all relative timing assumptions (e.g., isochronic forks) as well as the gate-level performance of any circuit designed with these templates. Library characterization can be utilized and asynchronous logic cells not found in standard-cell libraries, such as dual-rail domino logic and dynamic C-elements with staticizers, can be characterized in terms of both their timing and power. These values are a function of both input slew and output load and are preferably captured in an industry standard format, such as the Liberty&#x2122; file format, before being compatible with commercial STA tools. Using a characterized library, timing correctness and performance of an asynchronous circuit can be analyzed either through back-annotated simulations or preferably static analysis.

Static timing analysis of template-based asynchronous circuits

Techniques are described for generating asynchronous circuits (e.g., in the form of one or more netlists) for implementation, e.g., in integrated circuitry/chips. Embodiments are directed to asynchronous multi-level domino design template and several variants including a mixture of domino and single-rail data logic. The templates can provide high throughput, low latency, and area efficiency. A multi-level domino template is partitioned into pipeline stages in which each stage consists of potentially multiple-levels of domino logic controlled by a single controller that communicates with other controllers via handshaking. Each stage is composed of two parts: a data path and a control path. The data path implements the computational logic, both combinational and sequential using efficient dual-rail domino logic. The control path implements a unique four-phase handshake to ensure correctness and the preservation of logical dependencies between pipeline stages. The data path and controller interact through a small number of key control signals.

Multi-level domino, bundled data, and mixed templates

Techniques are described for generating asynchronous circuits from any arbitrary HDL representation of a synchronous circuit by automatically clustering the synthesized gates into pipeline stages that are then slack-matched to meet performance goals while minimizing area. Automatic pipelining can be provided in which the throughput of the overall design is not limited to the clock frequency or the level of pipelining in the original RTL specification. The techniques are applicable to many asynchronous design styles. A model and infrastructure can be designed that guides clustering to avoid the introduction of deadlocks and achieve a target circuit performance. Slack matching models can be used to take advantage of fanout optimizations of buffer trees that improve the quality of the results.

Clustering and fanout optimizations of asynchronous circuits

Techniques are described for converting netlists for synchronous circuits such as combinational modules, flip flops (or latches), and clock gating modules, to netlist of asynchronous modules. Processes including algorithms are described that bundle multiple modules in an enable domain, so that they are activated only if the incoming enable token to the enable domain has the UPDATE value. The modules can be clustered inside an enable domain, so that each cluster has a separate controller. The objective function of bundling and clustering can minimize power consumption with respect to a given cycle time. Exemplary embodiments can include a gated multilevel domino template.

Power aware asynchronous circuits

Methods and apparatus are described for optimizing a circuit design. A gate level circuit description corresponding to the circuit design is generated. The gate level circuit description includes a plurality of pipelines across a plurality of levels. Using a linear programming technique, a minimal number of buffers is added to selected ones of the pipelines such that a performance constraint is satisfied.

Logic synthesis of multi-level domino asynchronous pipelines

Decoding an encoded signal (for example, a turbo encoded signal, a block encoded signal or the like) is performed by demodulating the received encoded signal to produce soft information, and iteratively processing the soft information with one or more soft-in/soft-output (SISO) modules. At least one of the SISO modules uses a tree structure to compute forward and backward state metrics. More generally, iterative detection is performed by receiving an input signal corresponding to one or more outputs of a module whose soft-inverse can be computed by running the forward-backward algorithm on a trellis representation of the module, and determining the soft inverse of the module by computing forward and backward state metrics of the received input signal using a tree structure.

Reduced-latency soft-in/soft-out module

Methods and apparatus are described for facilitating physical synthesis of a circuit design. The circuit design includes a plurality cell instances organized hierarchically. Each cell instance corresponds schematically to one of a plurality of cell types. Transistors in each of the cell instances is sized with reference to an objective function thereby resulting in a first plurality of cell subtypes for each cell type. Each cell subtype corresponding to a particular cell type differs from all other cell subtypes corresponding to the particular cell type by at least one transistor dimension. Selected ones of the subtypes for at least one of the cell types are merged thereby resulting in a second plurality of subtypes for the at least one of the cell types. The second plurality of subtypes being fewer than the first plurality of subtypes. The merging of the selected subtypes achieves a balance between the objective function and a cost associated with maintaining the selected subtypes distinct.

Optimization of cell subtypes in a hierarchical design flow

Methods and apparatus are described for facilitating physical synthesis of an integrated circuit design. A set of paths between observable nodes in a netlist representing the circuit design is generated. Each path corresponds to a sequence of signal transitions. Transistors represented in the netlist are sized to attempt to meet a delay constraint for each path. The delay constraint corresponds to a unit delay times the number of signal transitions in the corresponding path. A plurality of individual delays of different durations are allocated among the transitions for at least one of the paths to meet the delay constraint. At least one of the individual delays exceeds the unit delay.

Methods and apparatus for facilitating physical synthesis of an integrated circuit design

A sequential decoder for decoding convolutional code is provided. The sequential decoder includes a computing device comprising a Fano technique. The Fano technique includes a plurality of variables that are normalized to change a point of reference of the technique. One of the variables is a current node metric. The variables are normalized such that the current node metric is set to approximately zero. Methods for using this decoder in applications that include periodic, hard deadlines such as real-time applications are also presented.

Sequential decoder for decoding of convolutional codes

Formal verification of a logic design through implicit enumeration of strongly connected components. The invention provides for efficient, cost-effective formal verification of logical circuits and systems using a method that is much less computationally expensive than other known methods. A digraph is recursively decomposed using reachability analysis. Non-trivial, strongly connected components derived through the use of the invention can be compared to expected behavior of a circuit or system. Alternatively, the invention can be applied to detect so-called &ldquo;bad cycles&rdquo; which are encountered in many formal verification problems.

Formal verification of a logic design through implicit enumeration of strongly connected components

Optimal parallelization of necessarily serial operations is performed by speculative parallel processing and propagation of serial marking signals to indicate valid data. An exemplary instruction marking circuit for a computer system implementing such optimization includes a series of columns, each column corresponding to one byte of a fixed length instruction line, and a length decoder in each column. Each length decoder receives a byte of the respective column, and performs a length decode independently of the other length decoders. The length decoder asserts a length signal indicative of an instruction length when the byte is the first byte of an instruction. A marking unit arrangement is coupled to the length decoders, and operates to mark each column containing a first byte of an instruction as a function of the length signals asserted by the length decoders.

Apparatus and method for parallel processing and self-timed serial

A self-timed instruction marking circuit includes a prefix handling system for processing instruction bytes having prefix bytes. Length decoders receive instruction data bytes, and perform length decoding independently of the other length decoders in the instruction marking circuit. A length decoder determines whether a byte being processed is a prefix byte to an instruction. If a length-affecting prefix byte is found, the length decoder signals a subsequent length decoder to indicate that a prefix byte has been found. The subsequent length decoder uses the prefix signal to appropriately length decode the byte being processed by the subsequent length decoder. Signals are provided to continue the self-timed marking process. Prefix handling may also be used in a multiple marking unit configuration of an instruction marking circuit.

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Peter A Beerel