Static timing analysis of template-based asynchronous circuits

Abstract

Effective timing and power characterization flows are described for asynchronous circuits. Verification can be provided for both relative-timing constraints as well as performance (e.g., throughput) targets using commercially-standard STA tools. Fully-automated scripts are developed that verify all relative timing assumptions (e.g., isochronic forks) as well as the gate-level performance of any circuit designed with these templates. Library characterization can be utilized and asynchronous logic cells not found in standard-cell libraries, such as dual-rail domino logic and dynamic C-elements with staticizers, can be characterized in terms of both their timing and power. These values are a function of both input slew and output load and are preferably captured in an industry standard format, such as the Liberty™ file format, before being compatible with commercial STA tools. Using a characterized library, timing correctness and performance of an asynchronous circuit can be analyzed either through back-annotated simulations or preferably static analysis.