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For the Inventor, By the Inventor

Dallas, TX, United States of America

Pervez Mirza Aziz

This inventor holds 62 USPTO granted patents and 8 published patent applications, primarily in Clock Data Recovery (CPC class H04L). Top assignees: Agere Systems Inc., Lsi Corporation, Nvidia Corporation. Active years: 2002-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Pervez Mirza Aziz. Retrieved from https://idiyas.com/inventor/pervez-mirza-aziz

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 62 

% Patents Active = 71.0

Average Co-Inventor Count = 2.4

ph-index = 11

Forward Citations = 730(Granted Patents)

Forward Citations (Not Self Cited) = 683(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Allentown, PA (US) (2002 - 2004)
  • Garland, TX (US) (2004 - 2009)
  • Dallas, TX (US) (2006 - 2024)

Company Filing History:

goldMedal32 out of 2,316 
 
Agere Systems Inc.
 patents
silverMedal13 out of 2,353 
 
Lsi Corporation
 patents
bronzeMedal11 out of 6,195 
 
Nvidia Corporation
 patents
4. 6 out of 1,813 
 
Avago Technologies General IP (Singapore) Pte. Ltd.
 patents

Years Active: 2002-2026

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Areas of Expertise:
Forward Error Correction
Equalization Adaptation
Clock Recovery
Data Eye Openings
Decision Feedback Equalization
Voltage Offset Cancellation
Nonlinear Distortion
Digital Phase Skew
Signal Detection
Jitter Tolerance
SERDES Systems
Latency Reduction
62 patents (USPTO):Explore Patents
1. 12744619 - Adapting communication link parameters using signal-to-noise (SNR) deviation metrics (2026-09-22),
2. 12580814 - Adapting forward error correction (FEC) or link parameters for improved post-FEC performance (2026-03-17),
3. 12267210 - Adapting forward error correction (FEC) or link parameters for improved post-FEC performance (2025-04-01),
4. 11985220 - Equalization adaptation schemes for high-speed links (2024-05-14),
5. 11665029 - Feed forward filter equalizer adaptation using a constrained filter tap coefficient value (2023-05-30),
6. 11646863 - Equalization adaptation schemes for high-speed links (2023-05-09),
7. 11611458 - Decision feed forward equalization for intersymbol interference cancelation (2023-03-21),
8. 11477004 - Clock data recovery convergence in modulated partial response systems (2022-10-18),
9. 11212073 - Clock data recovery convergence using signed timing injection (2021-12-28),
10. 11159304 - Clock data recovery mechanism (2021-10-26),
11. 10700846 - Clock data recovery convergence using signed timing injection (2020-06-30),
12. 9397674 - Clock recovery using quantized phase error samples using jitter frequency-dependent quantization thresholds and loop gains (2016-07-19),
13. 9294314 - Receiver having limiter-enhanced data eye openings (2016-03-22),
14. 9143367 - Clock and data recovery architecture with adaptive digital phase skew (2015-09-22),
15. 9106462 - Reduced power SERDES receiver using selective adaptation of equalizer parameters in response to supply voltage and operating temperature variations and technique for measuring same (2015-08-11),

Title: Innovations and Contributions of Pervez Mirza Aziz

Introduction

Pervez Mirza Aziz, based in Dallas, TX, is a prolific inventor with an impressive portfolio of 59 patents. His contributions to the field of integrated circuits, specifically in the area of high-speed communication links, have significantly advanced technology.

Latest Patents

Aziz's latest inventions showcase his expertise in equalization adaptation schemes for high-speed links. One notable patent involves an integrated circuit for a receiving link device that includes a processing device to detect when a receiver (RX) pre-cursor value is outside a specified threshold. This innovation generates tap messages with commands to adjust the corresponding transmitter (TX) pre-cursor value, enhancing the performance of the transmitting link device.

Another significant patent focuses on feed forward filter equalizer adaptation using constrained filter tap coefficient values. It presents a feed forward equalizer that adapts filter tap coefficients while applying constraints to ensure optimal performance. This adaptation process involves generating an equalized signal that includes estimated symbol values, which is crucial for effective data transmission.

Career Highlights

Throughout his career, Pervez Mirza Aziz has worked with prominent companies, including Agere Systems Inc. and LSI Corporation. His roles in these organizations have allowed him to contribute to high-impact projects and technologies, further establishing his reputation in the industry.

Collaborations

Aziz has collaborated with esteemed coworkers such as Mohammad Shafiul Mobin and Viswanath Annampedu. These partnerships have likely fostered innovation and creativity, leading to advancements in their shared projects.

Conclusion

Pervez Mirza Aziz's impressive record of patents and his contributions to the field of integrated circuits highlight his role as a leading innovator in high-speed communication technology. His work continues to influence the industry, paving the way for future advancements and inspiring new generations of inventors.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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