The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 2016

Filed:

Dec. 31, 2013
Applicant:

Lsi Corporation, San Jose, CA (US);

Inventors:

Pervez M. Aziz, Dallas, TX (US);

Shiva Prasad Kotagiri, Campbell, CA (US);

Sundeep Venkatraman, San Jose, CA (US);

Sunil Srinivasa, Santa Clara, CA (US);

Amaresh V. Malipatil, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03D 3/24 (2006.01); H03L 7/087 (2006.01); H03L 7/06 (2006.01);
U.S. Cl.
CPC ...
H03L 7/087 (2013.01); H03L 7/06 (2013.01);
Abstract

A clock and data recovery device includes a phase detector, a quantizer, and a loop filter. The phase detector produces a phase error samples at an output representing a phase difference between a phase-adjusted clock and an input data signal. The quantizer, coupled to the output of the phase detector and responsive to high threshold and low threshold values, produces a tri-valued quantized phase error samples at an output. The loop filter filters either the quantized phase error samples or the phase error samples to control the phase-controlled clock. A frequency detector, determining the frequency of jitter present in the input data signal, addresses a look-up table to provide the jitter-frequency dependent high and low threshold values and to control which phase error samples is processed by the loop filter. The frequency detector determines the jitter frequency by taking the ratio of peak values of low pass-filtered phase error samples.


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