The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 22, 2026
Filed:
Oct. 11, 2024
Nvidia Corporation, Santa Clara, CA (US);
Pervez Mirza Aziz, Dallas, TX (US);
Mohammad Shafiul Mobin, Murphy, TX (US);
NVIDIA Corporation, Santa Clara, CA (US);
Abstract
Technologies for optimizing post-FEC bit error rate (BER) performance of a Forward Error Correction (FEC) system are described. A controller is coupled to an FEC circuit and a receiver circuit. The controller receives equalized error data from the receiver circuit and determines, using the equalized error data and a nominal signal power, a signal-to-noise ratio (SNR) deviation metric, the SNR deviation metric being indicative of an estimated post-FEC BER of the FEC circuit. The controller adjusts, based on the SNR deviation metric, at least one of a FEC parameter of the FEC circuit or a link parameter of the receiver circuit to decrease the estimated post-FEC BER. This improves the post-FEC performance of the FEC circuit.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile