Agere Systems Inc.

Lsi Corporation

Nvidia Corporation

Avago Technologies General IP (Singapore) Pte. Ltd.

Pervez Mirza Aziz

Mohammad Shafiul Mobin

Viswanath Annampedu

Amaresh Virupanagouda Malipatil

Gregory W Sheets

Vishnu Balan

Lane Allen Smith

Adam Benjamin Healey

Vladimir Sindalovsky

Ye Liu

Hiroshi Kimura

Paul H Tracy

Sunil Srinivasa

Shiva Prasad Kotagiri

Donald Raymond Laturell

Shawn Michael Logan

Rohit Rathi

Akshay Shyam Pavagada Raghavendra

Lizhi Zhong

Geoffrey Zhang

Gary Schiessler

Hairong Gao

Necip Sayiner

Guo Hau Gau

Sundeep Venkatraman

Technologies for optimizing post-FEC bit error rate performance of a Forward Error Correction (FEC) system are described. A controller is coupled to an FEC circuit and a receiver circuit. The controller receives FEC symbol error data from the FEC circuit and determines, using the FEC symbol error data, a post-FEC correlated performance metric indicative of an estimated post-FEC BER of the FEC circuit. The controller adjusts, based on the post-FEC correlated performance metric, at least one of a FEC parameter of the FEC circuit or a link parameter of the receiver circuit to decrease the estimated post-FEC BER. This improves the post-FEC BER performance of the FEC circuit.

Adapting forward error correction (FEC) or link parameters for improved post-FEC performance

An integrated circuit for a receiving link device includes a processing device to detect, using an equalizer of the receiving link device, that a receiver (RX) pre-cursor value is outside of a threshold value based on a target RX tap value. The processing device further generates, based on the detecting, a plurality of tap messages having a plurality of up or down commands to one of decrease or increase a corresponding transmitter (TX) pre-cursor value of a transmitting link device. The processing device further causes the plurality of tap messages to be provided to a local transmitter to be transmitted to the transmitting link device. The plurality of tap messages is to cause the transmitting link device to adjust the corresponding TX pre-cursor value.

Equalization adaptation schemes for high-speed links

A feed forward equalizer including a first set of filter taps having a first set of filter tap coefficients to be adapted and a second set of one or more filter taps having one or more filter tap coefficients to be constrained. The feed forward equalizer includes an adaptation component to determine a set of adapted filter tap coefficient values corresponding to the first set of filter tap coefficients and a constraint function component to determine a constrained filter tap coefficient value for the second set of the one or more filter taps having the one or more filter tap coefficients to be constrained using a constraint function based on at least a portion of the set of adapted filter tap coefficient values. The feed forward equalizer generates, based at least in part on the constrained filter tap coefficient value, an equalized signal including a set of estimated symbol values.

Feed forward filter equalizer adaptation using a constrained filter tap coefficient value

A receiving link device includes a receiver (RX) to receive a data signal from a transmitting link device, the receiver including an equalizer to detect RX tap values and a processing device coupled to the receiver, the processing device to perform operations including: programming the receiver with information related to target RX tap values that are associated RX pre-cursors or RX post-cursors; detecting, using the equalizer, that an RX pre-cursor value is greater or less than a target RX tap value; generating, based on the detecting, a tap message including an up or a down command to decrease or increase a corresponding transmitter (TX) pre-cursor value of the transmitting link device; and causing the tap message to be provided to a local transmitter to be transmitted to a remote receiver of the transmitting link device, which causes the transmitting link device to adjust the corresponding TX pre-cursor value.

A receiver includes a decision feed forward equalization (DFFE) system coupled to a partial response (PR) system. The partial response system generates, based on a digital signal that includes pre-cursor intersymbol interference (ISI) and post-cursor ISI introduced by a communication channel, a detected signal including a set of detected symbol values. The detected signal is equalized to a partial response. The DFFE system includes a PR inverter to generate a set of estimated transmitted symbol values based on the set of detected symbol values and DFFE circuitry to cancel the pre-cursor ISI and the post-cursor ISI from the detected signal using the set of estimated transmitted symbols and a set of tap coefficients to obtain a compensated signal and a set of compensated symbol values.

Decision feed forward equalization for intersymbol interference cancelation

A clock data recovery circuit detects illegal decisions for received data, accumulates a phase gradient for the data, determines a number of the illegal decisions in a configured window for receiving the data, and if the number of the illegal decisions exceeds a pre-defend number in the window, applies a sum of the accumulated phase gradient and a phase increment having a sign of the accumulated phase gradient to a clock circuit for the data receiver.

Clock data recovery convergence in modulated partial response systems

A system for data and clock recovery includes a timing error detector, a phase detector, and a phase increment injector. The phase increment injector may be used to determine an increment to affect an output of the phase detector or a clocking element. A sign of the increment is determined from a sign or direction of an accumulated version of a clock and data recovery gradient value.

Clock data recovery convergence using signed timing injection

A clock data recovery (CDR) mechanism qualifies symbols received from the data detector prior to using those symbols to compute a timing gradient. The disclosed CDR mechanism analyzes one or more recently received symbols to determine whether the current symbol should be used in computing the time gradient. When configured with a Mueller-Muller phase detector, the timing gradient for the received signal is set to zero if the current symbol is a &#x2212;2 or a +2 and the previous symbol is non-zero. Otherwise, the Mueller-Muller timing gradient is evaluated in the traditional manner. When configured with a minimum mean-squared error phase detector, the timing gradient for the received signal is set to zero if the previous symbol is non-zero. Otherwise, the minimum mean-squared error timing gradient is evaluated in the traditional manner.

Clock data recovery mechanism

A clock and data recovery device includes a phase detector, a quantizer, and a loop filter. The phase detector produces a phase error samples at an output representing a phase difference between a phase-adjusted clock and an input data signal. The quantizer, coupled to the output of the phase detector and responsive to high threshold and low threshold values, produces a tri-valued quantized phase error samples at an output. The loop filter filters either the quantized phase error samples or the phase error samples to control the phase-controlled clock. A frequency detector, determining the frequency of jitter present in the input data signal, addresses a look-up table to provide the jitter-frequency dependent high and low threshold values and to control which phase error samples is processed by the loop filter. The frequency detector determines the jitter frequency by taking the ratio of peak values of low pass-filtered phase error samples.

Clock recovery using quantized phase error samples using jitter frequency-dependent quantization thresholds and loop gains

A communication system having a receiver with a linear path and a nonlinear path. As the receiver receives a data signal, it adaptively equalizes the received signal, and amplitude-limits the equalized signal in the nonlinear path using a saturable amplifier limiter or the like. A slicer extracts data from the limited equalized received signal. In the linear path, a clock recovery circuit generates a clock signal from the equalized received signal. A delay circuit in the linear path at least partially compensates for propagation delay in the limiter. Having the clock recovery occur in other than the nonlinear path, a low jitter clock is generated. The limiter enhances the vertical opening of the data eye by increasing the rise and fall times of the limited signal, providing more noise margin for the slicer to operate with and a greater timing margin in which to sample the sliced data.

Receiver having limiter-enhanced data eye openings

In described embodiments, a method for producing sample decisions with a digital signal processing-based SERDES device includes converting an analog signal to a digital signal, equalizing the digital signal, selecting inputs for a phase detector in a main CDR loop, computing a phase difference signal, producing a phase skew to signals for a last equalization stage by a first interpolation filter bank, generating a control signal to control the phase provided by the first interpolation filter bank by a phase skew adaptation loop, and updating the phase skew values to generate a resulting decision. A device includes a first interpolation filter bank inserted between the equalization stages is configured to generate phase skew signals to a last equalization stage and a phase skew loop responsive to the last equalization stage is configured to adjust the phase skew provided by the first interpolation filter bank.

Clock and data recovery architecture with adaptive digital phase skew

A method for facilitating acquisition of a received reference clock signal in a CDR system includes steps of: initializing an integral register in a digital loop filter of the CDR system by setting a current value of the integral register to a first value; determining a number of mislock events occurring in a CDR loop of the CDR system, a mislock event being indicative of an unlocked state of the CDR loop; adjusting the current value of the integral register, when the number of mislock events is non-zero, by a second value to generate a new current value, the second value being a function of a negation of the current value of the integral register; and repeating the steps of determining the number of mislock events and adjusting the current value of the integral register until the number of mislock events is zero.

Enhanced clock and data recovery acquisition in the presence of large frequency offsets

Described embodiments include a process and apparatus that takes into account the operating voltage and temperature (VT) variations of a SERDES receiver implemented in an integrated circuit (IC) or system-on-chip (SoC). An analog equalizer (AEQ) adaptation loop and a decision feedback equalizer (DFE) adaptation loop are disabled after the loops have converged or stabilized the parameters of the AEQ and DFE. While the AFE and DFE adaptation loops are disabled, certain monitor coefficients related to signals corrected by the AFE and DFE are adapted and metrics derived therefrom are generated. The metrics are compared to threshold values to check if they have sufficiently changed over time to warrant re-enabling of the AFE and DFE adaptation loops.

Reduced power SERDES receiver using selective adaptation of equalizer parameters in response to supply voltage and operating temperature variations and technique for measuring same

A receiver containing analog circuitry that generates distortion, a distortion compensation circuit coupled to an output of the analog circuitry, and a slicer, operating as a signal peak detector, coupled to the distortion compensation circuitry. The distortion compensation circuit has a subtractor, a function generator, and a weighting circuit. The subtractor has a first input coupled to the output of the analog circuitry, a second input, and an output. The function generator has an input coupled to the first input of the subtractor. The weighting circuit, responsive to a weighting coefficient, is coupled between an output of the function circuit and the second input of the first subtractor. The function generator has a transfer function with a third-power term and the weighting coefficient is set to a value based on the level of the signal peaks that will least partially reduce distortion in signals on the output of the subtractor.

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Dallas, TX, United States of America

Pervez Mirza Aziz