The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2016

Filed:

Mar. 28, 2014
Applicant:

Lsi Corporation, Milpitas, CA (US);

Inventors:

Mohammad S. Mobin, Orefield, PA (US);

Pervez M. Aziz, Dallas, TX (US);

Ye Liu, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03H 7/30 (2006.01); H03H 7/40 (2006.01); H03K 5/159 (2006.01); H04L 25/03 (2006.01); H04L 7/10 (2006.01); H04L 27/00 (2006.01);
U.S. Cl.
CPC ...
H04L 25/03057 (2013.01); H04L 7/10 (2013.01); H04L 25/03063 (2013.01); H04L 27/0002 (2013.01); H04L 2025/03636 (2013.01);
Abstract

A communication system having a receiver with a linear path and a nonlinear path. As the receiver receives a data signal, it adaptively equalizes the received signal, and amplitude-limits the equalized signal in the nonlinear path using a saturable amplifier limiter or the like. A slicer extracts data from the limited equalized received signal. In the linear path, a clock recovery circuit generates a clock signal from the equalized received signal. A delay circuit in the linear path at least partially compensates for propagation delay in the limiter. Having the clock recovery occur in other than the nonlinear path, a low jitter clock is generated. The limiter enhances the vertical opening of the data eye by increasing the rise and fall times of the limited signal, providing more noise margin for the slicer to operate with and a greater timing margin in which to sample the sliced data.


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