IDiyas

For the Inventor, By the Inventor

Los Angeles, CA, United States of America

Paul B Hashimoto

USPTO Granted Patents = 16

Average Co-Inventor Count = 4.6

ph-index = 8

Forward Citations = 117(Granted Patents)


Company Filing History:

goldMedal16 out of 2,068 
 
Hrl Laboratories, LLC
 patents

Years Active: 2004-2016

Loading Chart...
16 patents (USPTO):Explore Patents
1. 9252247 - Apparatus and method for reducing the interface resistance in GaN Heterojunction FETs (2016-02-02),
2. 8766321 - Self-aligned sidewall gate GaN HEMT (2014-07-01),
3. 8748244 - Enhancement and depletion mode GaN HMETs on the same substrate (2014-06-10),
4. 8686473 - Apparatus and method for reducing the interface resistance in GaN heterojunction FETs (2014-04-01),
5. 8383471 - Self aligned sidewall gate GaN HEMT (2013-02-26),
6. 8030688 - Ohmic metal contact protection using an encapsulation layer (2011-10-04),
7. 7700974 - Process for fabricating ultra-low contact resistances in GaN-based devices (2010-04-20),
8. 7598131 - High power-low noise microwave GaN heterojunction field effect transistor (2009-10-06),
9. 7566916 - Ohmic metal contact and channel protection in GaN devices using an encapsulation layer (2009-07-28),
10. 7470941 - High power-low noise microwave GaN heterojunction field effect transistor (2008-12-30),
11. 7247893 - Non-planar nitride-based heterostructure field effect transistor (2007-07-24),
12. 7098490 - GaN DHFET (2006-08-29),
13. 6897137 - Process for fabricating ultra-low contact resistances in GaN-based devices (2005-05-24),
14. 6884704 - Ohmic metal contact and channel protection in GaN devices using an encapsulation layer (2005-04-26),
15. 6852615 - Ohmic contacts for high electron mobility transistors and a method of making the same (2005-02-08),

Title: The Innovative Contributions of Paul B Hashimoto

Introduction

Paul B Hashimoto is a prominent inventor based in Los Angeles, CA. He has made significant contributions to the field of semiconductor technology, particularly in the development of Gallium Nitride (GaN) devices. With a total of 16 patents to his name, Hashimoto continues to push the boundaries of innovation in his field.

Latest Patents

Among his latest patents is the "Apparatus and method for reducing the interface resistance in GaN Heterojunction FETs." This invention addresses the challenge of interface resistance between the source/drain and gate of an HFET by engineering the bandgap of the 2DEG outside the gate region. By increasing the charge density, the resistance can be significantly reduced. Additionally, the use of an n+GaN Cap layer over the channel layer and barrier layer further enhances performance. This technique is applicable to both depletion and enhancement mode HFETs.

Another notable patent is the "Self-aligned sidewall gate GaN HEMT." This method involves a multi-layer growth process on a substrate, followed by the deposition of dielectric films to create a sidewall gate. The innovative design allows for a sidewall gate length of less than 50 nm, showcasing Hashimoto's expertise in advanced semiconductor fabrication techniques.

Career Highlights

Paul B Hashimoto is currently employed at HRL Laboratories, LLC, where he continues to develop cutting-edge technologies. His work has been instrumental in advancing GaN technology, which is crucial for high-frequency and high-power applications.

Collaborations

Throughout his career, Hashimoto has collaborated with talented individuals such as Miroslav Micovic and Tahir Hussain. These partnerships have fostered a creative environment that encourages innovation and the sharing of ideas.

Conclusion

Paul B Hashimoto's contributions to the field of semiconductor technology are noteworthy and impactful. His innovative patents and collaborative efforts continue to shape the future of GaN devices. His work exemplifies the spirit of innovation that drives progress in technology.

This text is generated by artificial intelligence and may not be accurate.
Please report any incorrect information to support@idiyas.com
Loading…