The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2016

Filed:

Jan. 10, 2014
Applicant:

Hrl Laboratories, Llc, Malibu, CA (US);

Inventors:

Miroslav Micovic, Thousand Oaks, CA (US);

Andrea Corrion, Thousand Oaks, CA (US);

Keisuke Shinohara, Thousand Oaks, CA (US);

Peter J Willadsen, Thousand Oaks, CA (US);

Shawn D Burnham, Oxnard, CA (US);

Hooman Kazemi, Thousand Oaks, CA (US);

Paul B Hashimoto, Los Angeles, CA (US);

Assignee:

HRL Laboratories, LLC, Malibu, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/739 (2006.01); H01L 21/338 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66916 (2013.01);
Abstract

The interface resistance between the source/drain and gate of an HFET may be significantly reduced by engineering the bandgap of the 2DEG outside a gate region such that the charge density is substantially increased. The resistance may be further reduced by using an n+GaN Cap layer over the channel layer and barrier layer such that a horizontal surface of the barrier layer beyond the gate region is covered by the n+GaN Cap layer. This technique is applicable to depletion and enhancement mode HFETs.


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