The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 06, 2009
Filed:
Nov. 05, 2008
Miroslav Micovic, Newbury Park, CA (US);
Tahir Hussain, Calabasas, CA (US);
Paul Hashimoto, Los Angeles, CA (US);
Mike Antcliffe, Los Angeles, CA (US);
Miroslav Micovic, Newbury Park, CA (US);
Tahir Hussain, Calabasas, CA (US);
Paul Hashimoto, Los Angeles, CA (US);
Mike Antcliffe, Los Angeles, CA (US);
HRL Laboratories, LLC, Malibu, CA (US);
Abstract
A method for fabricating heterojunction field effect transistors (HFET) and a family of HFET layer structures are presented. In the method, a step of depositing a HFET semiconductor structure onto a substrate is performed. Next, a photoresist material is deposited. Portions of the photoresist material are removed corresponding to source and drain pad pairs. A metal layer is deposited onto the structure, forming source pad and drain pad pairs. The photoresist material is removed, exposing the structure in areas other than the source and drain pad pairs. Each source and drain pad pair has a corresponding exposed area. The structure is annealed and devices are electrically isolated. The exposed area of each device is etched to form a gate recess and a gate structure is formed in the recess. Semiconductor layer structures for GaN/AlGaN HFETs are also presented.