logo

For the Inventor, By the Inventor

Bengaluru, India

Parvinder Kumar Rana

This inventor holds 26 USPTO granted patents and 3 published patent applications, primarily in Memory Device Engineering. Top assignees: Samsung Electronics Co., Ltd., Texas Instruments Corporation, Samsung Electronics Ltd.. Active years: 2012-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Parvinder Kumar Rana. Retrieved from https://idiyas.com/inventor/parvinder-kumar-rana

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 26 

% Patents Active = 100.0

Average Co-Inventor Count = 3.6

ph-index = 4

Forward Citations = 63(Granted Patents)


Location History:

  • Ambala, IN (2012)
  • Ambala Cantt., IN (2012)
  • Karnataka, IN (2020)
  • Hwansung-si, KR (2018 - 2022)
  • Bengaluru, IN (2012 - 2023)

Company Filing History:

goldMedal18 out of 132,108 
 
Samsung Electronics Co., Ltd.
 patents
silverMedal7 out of 29,869 
 
Texas Instruments Corporation
 patents
bronzeMedal1 out of 6,034 
 
Samsung Electronics Ltd.
 patents

Years Active: 2012-2026

Loading Chart...
Areas of Expertise:
Static Random-Access Memory
FinFET Design
Power Reduction
Bitline Precharge
Voltage Compensation
Delay Tuning
Edge Triggered Flip-Flop
Sense Amplifier
Fabrication Variations
Clock Generator
SoC Device
Margin Testing
26 patents (USPTO):Explore Patents
1. 12567461 - Memory device and operation to reduce impact of parasitic wire resistance and capacitance (2026-03-03),
2. 11790982 - Circuits for power down leakage reduction in random-access memory (2023-10-17),
3. 11776623 - Bitline precharge system for a semiconductor memory device (2023-10-03),
4. 11410720 - Bitline precharge system for a semiconductor memory device (2022-08-09),
5. 11290092 - Level shifter circuits (2022-03-29),
6. 11271011 - Method for high performance standard cell design techniques in FinFET based library using local layout effects (LLE) (2022-03-08),
7. 11017848 - Static random-access memory (SRAM) system with delay tuning and control and a method thereof (2021-05-25),
8. 10998018 - Apparatus and methods for compensating for variations in fabrication process of component(s) in a memory (2021-05-04),
9. 10803929 - Static random-access memory with virtual banking architecture, and system and method including the same (2020-10-13),
10. 10748932 - Method for high performance standard cell design techniques in FinFET based library using local layout effects (LLE) (2020-08-18),
11. 10715118 - Flip-flop with single pre-charge node (2020-07-14),
12. 10672443 - Methods and systems for performing decoding in finFET based memories (2020-06-02),
13. 10665295 - Static random-access memory with virtual banking architecture, and system and method including the same (2020-05-26),
14. 10651850 - Low voltage tolerant ultra-low power edge triggered flip-flop for standard cell library (2020-05-12),
15. 10566959 - Sense amplifier flip-flop and method for fixing setup time violations in an integrated circuit (2020-02-18),

Title: Innovations by Parvinder Kumar Rana: A Journey Through Patents and Collaborations

Introduction: Parvinder Kumar Rana, based in Bengaluru, India, is a prominent inventor with an impressive portfolio of 25 patents. His groundbreaking work primarily focuses on advancements in semiconductor memory technology. His inventions aim to address critical challenges within the industry, particularly in leakage reduction and efficient memory operations.

Latest Patents: Among his latest patents, Rana developed a "Circuits for power down leakage reduction in random-access memory" which presents a novel wordline driver circuit designed to minimize leakage during power down mode. This includes a pre-driver stage featuring both header and footer components, integrating multiple switches for enhanced voltage control across wordlines. Another significant patent is the "Bitline precharge system for a semiconductor memory device," which outlines a system comprising a voltage comparator circuit that outputs a reference voltage based on input wordline and peripheral power supply levels. This system further ensures efficient precharging of the bitlines during read and write operations, streamlining memory device performance.

Career Highlights: Parvinder Kumar Rana has made significant contributions during his tenure at leading technology firms such as Samsung Electronics and Texas Instruments Corporation. His expertise in semiconductor design and memory technologies has been pivotal in shaping innovations that cater to the evolving demands of the tech landscape.

Collaborations: Throughout his career, Rana has collaborated with esteemed colleagues including Lava Kumar Pulluru and Manish Chandra Joshi. These collaborations have facilitated the exchange of innovative ideas and practices, further enhancing the quality and impact of his inventions.

Conclusion: Parvinder Kumar Rana's relentless pursuit of innovation in semiconductor technologies is reflected in his extensive patent portfolio. His latest inventions not only showcase his technical prowess but also contribute significantly to advancements in random-access memory systems. As the tech industry evolves, his work will undoubtedly play a crucial role in shaping the future of memory device technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…