The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 29, 2022

Filed:

Feb. 15, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Ankur Gupta, Bangalore, IN;

Lava Kumar Pulluru, Bangalore, IN;

Parvinder Kumar Rana, Bangalore, IN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/40 (2006.01); H03K 3/356 (2006.01); H03K 19/0185 (2006.01); G11C 11/419 (2006.01); G11C 11/412 (2006.01);
U.S. Cl.
CPC ...
H03K 3/356113 (2013.01); G11C 11/412 (2013.01); G11C 11/419 (2013.01); H03K 3/356182 (2013.01); H03K 19/018521 (2013.01);
Abstract

An apparatus includes a NMOS transistor having a drain, a first PMOS transistor having a drain connected to the drain of the NMOS transistor, a level shifter having an input and an output, the input of the level shifter being connected to the drain of the NMOS transistor and the drain of the first PMOS transistor, a first digital logic circuit having a drain and a gate, a first inverter having an input connected to the Aoutput of the level shifter and the drain of the first digital logic circuit, and a second digital logic circuit having an output connected to the gate of the first digital logic circuit, at least one condition being set in the apparatus during a read operation.


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