The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 12, 2020
Filed:
Mar. 25, 2019
Samsung Electronics Co., Ltd., Suwon-si, KR;
Sajal Mittal, Bengaluru, IN;
Jaskaran Singh Bhatia, New Delhi, IN;
Rajeela Deshpande, Bengaluru, IN;
Parvinder Kumar Rana, Bengaluru, IN;
Nikhila C M, Bengaluru, IN;
Abhishek Ghosh, Bengaluru, IN;
Rahul Kataria, Bengaluru, IN;
SAMSUNG ELECTRONICS CO., LTD., Suwon-si, KR;
Abstract
A method and a flip-flop for designing low power integrated circuits (IC's). The method includes receiving at least one of a clock signal, a data signal, and a complimentary data signal. The complimentary data signal is produced by an input data inverter present in the flip-flop. Further, the method includes generating at least one master internal signal based on the received at least one of the clock signal, the data signal, and the complimentary data signal, when the clock signal is at a low logic level. Further, the method includes generating at least one slave internal signal based on at least one of the received clock signal and the generated at least one master internal signal, when the clock signal is at a high logic level. Further, the method includes generating an output signal based on the generated at least one slave internal signal.