The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 18, 2020
Filed:
Feb. 14, 2019
Samsung Electronics Co., Ltd., Suwon-si, KR;
Sajal Mittal, Bengaluru, IN;
Parvinder Kumar Rana, Bengaluru, IN;
Abhishek Ghosh, Bengaluru, IN;
Rajeela Deshpande, Bengaluru, IN;
SAMSUNG ELECTRONICS CO., LTD., Suwon-si, KR;
Abstract
A method and a sense amplifier flip-flop (SAFF) for fixing setup time violations in an integrated circuit (IC) design. The SAFF includes a master latch coupled to a slave latch, wherein the master latch includes a sense amplifier and the SAFF is configured with an equal number of p-type metal oxide semiconductor (PMOS) transistors and n-type metal oxide semiconductor (NMOS) transistors to reduce block area of an integrated circuit (IC). The method includes receiving a clock signal, receiving a data signal, applying the data signal to the sense amplifier when the clock signal is at a low level, wherein a portion of the sense amplifier is responsive to the inverted clock signal, storing a value of the data signal in the slave latch when the clock signal transitions from the low level to the high level, and providing an output signal from the slave latch.