The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2020

Filed:

Aug. 13, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Shyam Agarwal, Bangalore, IN;

Sandeep B V, Bangalore, IN;

Shreyas Samraksh Jayaprakash, Karnataka, IN;

Abhishek Kumar Ghosh, Bangalore, IN;

Parvinder Kumar Rana, Bangalore, IN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/41 (2006.01); H03K 3/3562 (2006.01); H01L 27/11 (2006.01); H03K 19/017 (2006.01); H03K 3/012 (2006.01);
U.S. Cl.
CPC ...
H03K 3/35625 (2013.01); G11C 11/41 (2013.01); H01L 27/1104 (2013.01); H03K 3/012 (2013.01); H03K 19/01728 (2013.01);
Abstract

Various example embodiments herein disclose a flip-flop including a master latch comprising one of: a plurality of P-type metal-oxide-semiconductor (PMOS) and a plurality of N-type metal-oxide-semiconductor (NMOS). A slave latch includes one of: a plurality of PMOS and a plurality of NMOS. An inverted clock signal input is communicatively connected with the master latch and the slave latch. The master latch includes a single pre-charge node. The single pre-charge node sets up a data capture path in the flip flop. Data is stored in the master latch and the slave latch via the pre-charge node.


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