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For the Inventor, By the Inventor

San Jose, CA, United States of America

Nui Chong

LinkedIn
USPTO Granted Patents = 20 

 

Average Co-Inventor Count = 3.1

ph-index = 4

Forward Citations = 79(Granted Patents)


Location History:

  • Cupertino, CA (US) (2010 - 2019)
  • San Jose, CA (US) (2006 - 2024)

Company Filing History:

goldMedal18 out of 5,002 
 
Xilinx, Inc.
 patents
silverMedal2 out of 755 
 
Lattice Semiconductor Corporation
 patents

Years Active: 2006-2024

where 'Filed Patents' based on already Granted Patents

20 patents (USPTO):
1. 12045469 - Single event upset tolerant memory device (2024-07-23),
2. 11650249 - Wafer testing and structures for wafer testing (2023-05-16),
3. 11585854 - Runtime measurement of process variations and supply voltage characteristics (2023-02-21),
4. 11164749 - Warpage reduction (2021-11-02),
5. 11119146 - Testing of bonded wafers and structures for testing bonded wafers (2021-09-14),
6. 11114344 - IC die with dummy structures (2021-09-07),
7. 11054461 - Test circuits for testing a die stack (2021-07-06),
8. 10756711 - Integrated circuit skew determination (2020-08-25),
9. 10692837 - Chip package assembly with modular core dice (2020-06-23),
10. 10629512 - Integrated circuit die with in-chip heat sink (2020-04-21),
11. 10566050 - Selectively disconnecting a memory cell from a power supply (2020-02-18),
12. 10379155 - In-die transistor characterization in an IC (2019-08-13),
13. 10103139 - Method and design of low sheet resistance MEOL resistors (2018-10-16),
14. 10043724 - Using an integrated circuit die for multiple devices (2018-08-07),
15. 9177634 - Two gate pitch FPGA memory cell (2015-11-03),

Title: Innovations and Contributions of Nui Chong in the Semiconductor Industry

Introduction

Nui Chong is a prominent inventor located in San Jose, California, known for his significant contributions to the field of semiconductor technology. With a remarkable portfolio of 20 patents, he has been at the forefront of innovation, developing cutting-edge solutions that enhance memory devices and testing methodologies.

Latest Patents

Among Nui Chong's latest patents is a breakthrough titled "Single Event Upset Tolerant Memory Device." This invention describes a memory device that improves Single Event Upset (SEU) resistance by leveraging high ratio column multiplexers. The device is designed for use in integrated circuit die and chip packages, and it incorporates two arrays of semiconductor memory cells alongside multiple sense amplifiers for optimal performance.

Another noteworthy patent is titled "Wafer Testing and Structures for Wafer Testing." This patent relates to enhanced methodologies for wafer testing, including techniques for applying power to specific pads on a wafer, connected to a device under test. The innovative structures and methods described help improve the effectiveness of testing in semiconductor devices.

Career Highlights

Nui Chong has worked with esteemed companies in the semiconductor industry, including Xilinx, Inc. and Lattice Semiconductor Corporation. His experience at these companies has allowed him to refine his skills in developing advanced semiconductor solutions and contribute to projects that push the boundaries of current technologies.

Collaborations

Throughout his career, Nui has collaborated with talented professionals, including coworkers such as Cheang-Whang Chang and Henley Liu. These partnerships have facilitated the exchange of ideas and the pooling of expertise, enabling the successful development of innovative semiconductor technologies.

Conclusion

Nui Chong's contributions to the semiconductor industry through his numerous patents and collaborative efforts underscore his role as a key innovator. With each invention, he continues to pave the way for advancements in memory devices and wafer testing, significantly impacting the future of technology.

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