The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 02, 2021
Filed:
Sep. 16, 2019
Applicant:
Xilinx, Inc., San Jose, CA (US);
Inventors:
Nui Chong, San Jose, CA (US);
Hui-Wen Lin, San Jose, CA (US);
Assignee:
XILINX, INC., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/302 (2006.01); H01L 23/498 (2006.01); H01L 21/67 (2006.01); H01L 23/00 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/302 (2013.01); H01L 21/67069 (2013.01); H01L 21/67075 (2013.01); H01L 23/49822 (2013.01); H01L 23/562 (2013.01); H01L 29/7843 (2013.01);
Abstract
Examples described herein provide a method for reducing warpage when stacking semiconductor substrates. In an example, a first substrate is bonded with a second substrate to form a stack. The first substrate comprises a first semiconductor substrate, and the second substrate comprises a second semiconductor substrate. The second semiconductor substrate is thinned, and a first trench is etched into a backside of the thinned second semiconductor substrate. A first stressed material is deposited into the first trench.