The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 06, 2021
Filed:
Mar. 12, 2019
Xilinx, Inc., San Jose, CA (US);
Nui Chong, San Jose, CA (US);
Amitava Majumdar, San Jose, CA (US);
Cheang-Whang Chang, Mountain View, CA (US);
Henley Liu, San Jose, CA (US);
Myongseob Kim, Pleasanton, CA (US);
Albert Shih-Huai Lin, Mountain View, CA (US);
XILINX, INC., San Jose, CA (US);
Abstract
Device(s) and method(s) related generally to a wafer or die stack are disclosed. In one such device, a die stack of two or more integrated circuit dies has associated therewith test circuits corresponding to each level of the die stack each with a set of pads. A test data-input path includes being from: a test data-in pad through a test circuit to a test data-out pad of each of the test circuits; and the test data-out pad to the test data-in pad between consecutive levels of the test circuits. Each of the set of pads includes the test data-in pad and the test data-out pad respectively thereof. A test data-output path is coupled to the test data-out pad of a level of the levels.