The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 16, 2018
Filed:
Jul. 07, 2015
Applicant:
Xilinx, Inc., San Jose, CA (US);
Inventors:
Nui Chong, Cupertino, CA (US);
Jae-Gyung Ahn, Pleasanton, CA (US);
Ping-Chin Yeh, San Jose, CA (US);
Cheang-Whang Chang, Mountain View, CA (US);
Assignee:
XILINX, INC., San Jose, CA (US);
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/00 (2006.01); H01L 23/62 (2006.01); H01L 27/07 (2006.01); H01L 23/522 (2006.01); H01L 27/06 (2006.01); H01L 49/02 (2006.01); H01L 21/283 (2006.01); H01L 21/76 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0738 (2013.01); H01L 21/283 (2013.01); H01L 21/76 (2013.01); H01L 23/5228 (2013.01); H01L 27/0629 (2013.01); H01L 28/24 (2013.01); H01L 27/0207 (2013.01);
Abstract
An integrated circuit structure includes: a semiconductor substrate; a shallow trench isolation (STI) region in the semiconductor substrate; one or more active devices formed on the semiconductor substrate; and a resistor array having a plurality of resistors disposed above the STI region; wherein the resistor array comprises a portion of one or more interconnect contact layers that are for interconnection to the one or more active devices.