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For the Inventor, By the Inventor

San Jose, CA, United States of America

Nicolas J Camilleri

This inventor holds 10 USPTO granted patents. Top assignee: Xilinx, Inc.. Active years: 1999-2010.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Nicolas J Camilleri. Retrieved from https://idiyas.com/inventor/nicolas-j-camilleri

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 10

% Patents Active = 90.0

Average Co-Inventor Count = 2.3

ph-index = 8

Forward Citations = 466(Granted Patents)


Location History:

  • San Jose, CA (US) (1999 - 2002)
  • Santa Cruz, CA (US) (2002 - 2010)

Company Filing History:

goldMedal10 out of 5,108 
 
Xilinx, Inc.
 patents

Years Active: 1999-2010

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10 patents (USPTO):Explore Patents
1. 7669163 - Partial configuration of a programmable gate array using a bus macro and coupling the third design (2010-02-23),
2. 7024651 - Partial reconfiguration of a programmable gate array using a bus macro (2006-04-04),
3. 6732347 - Clock template for configuring a programmable gate array (2004-05-04),
4. 6462579 - Partial reconfiguration of a programmable gate array using a bus macro (2002-10-08),
5. 6434642 - FIFO memory system and method with improved determination of full and empty conditions and amount of data stored (2002-08-13),
6. 6405269 - FIFO memory including a comparator circuit for determining full/empty conditions using mode control and carry chain multiplexers (2002-06-11),
7. 6401148 - FIFO memory system and method with improved determination of amount of data stored using a binary read address synchronized to a write clock (2002-06-04),
8. 6389490 - FIFO memory system and method with improved generation of empty and full control signals in one clock cycle using almost empty and almost full signals (2002-05-14),
9. 6107827 - FPGA CLE with two independent carry chains (2000-08-22),
10. 5963050 - Configurable logic element with fast feedback paths (1999-10-05),

Title: Innovations of Nicolas J Camilleri

Introduction

Nicolas J Camilleri is a prominent inventor based in San Jose, CA, known for his significant contributions to the field of programmable gate arrays. With a total of 10 patents to his name, Camilleri has made remarkable advancements in the technology that underpins modern electronic devices.

Latest Patents

His latest patents include innovative methods for the partial configuration of a programmable gate array (FPGA) using a bus macro. One of his notable inventions describes a method of partially reconfiguring an FPGA with interdesign routing, allowing for efficient use of design areas within the FPGA. This method involves implementing a first configuration data set that utilizes a bus interface to connect different designs, enhancing the flexibility and functionality of the FPGA. Another patent focuses on a bus macro that serves as a routing resource for partial reconfiguration, which includes a set of gates that control signal routing between design areas, optimizing the performance of the FPGA.

Career Highlights

Nicolas J Camilleri has built a successful career at Xilinx, Inc., a leading company in the field of programmable logic devices. His work has been instrumental in advancing the capabilities of FPGAs, making them more adaptable and efficient for various applications.

Collaborations

Throughout his career, Camilleri has collaborated with notable colleagues, including Edward S McGettigan and Steven P Young. These partnerships have contributed to the innovative projects and patents that have emerged from his work.

Conclusion

Nicolas J Camilleri's contributions to the field of programmable gate arrays have established him as a key figure in the industry. His innovative patents and collaborations continue to influence the development of advanced electronic technologies.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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