Fifo memory system and method with improved generation of empty and full control signals in one clock cycle using almost empty and almost full signals

Abstract

A first in, first out (FIFO) memory system and method in which the full or empty condition of the FIFO memory is detected before the FIFO memory is actually full or empty, thereby allowing the generation of FULL or EMPTY control signals immediately after a last data value is written into or from the FIFO memory. An almost-empty condition, is detected by comparing the read address and write address values. When the read and write address values indicate that one data value remains in the FIFO memory and a read operation is about to be performed, an ALMOST_EMPTY control signal is applied to a data input terminal of a first register that is clocked by a read clock signal. The ALMOST_EMPTY control signal is latched by the first register at the next rising edge of a read clock signal, thereby causing the register to generate a high EMPTY control signal in the same read clock cycle during which the last data value is read from the FIFO memory. Similarly, an almost-full condition, is also detected by comparing the read address and write address values. By preventing a write address counter from “catching up” to a read address counter, the determination of FULL and EMPTY conditions is greatly simplified. The FIFO memory system may also include binary-to-Gray-code converters as well as a write synchronization circuit for synchronizing a binary read address to a write clock signal to provide an accurate indication of the amount of data stored in the FIFO memory.