Fifo memory including a comparator circuit for determining full/empty conditions using mode control and carry chain multiplexers

Abstract

A comparator circuit for detecting full and empty conditions in a first-in first-out (FIFO) memory system. The comparator circuit includes two-input logic circuits for comparing selected read and write addresses. An almost-empty condition is detected by comparing a next-to-be-used read address value with a currently-used write address value. When these address values are equal, high logic signals are passed by a set of mode control multiplexers to the select terminals of a series of carry chain multiplexers, thereby causing a high logic value to be transmitted to a data input terminal of a first register. The first register latches the high logic signal at the next rising edge of the read clock signal, thereby generating a high EMPTY control signal immediately after a final data value is read from the memory. The high EMPTY control signal causes the mode control multiplexers to pass logic signals generated by comparing a current read address value and a current write address value, which are equal when the memory is in the empty condition. The full condition is determined in a similar fashion, using a second carry chain to transmit logic signals related to both an almost-full and the full condition.