The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 05, 1999
Filed:
Mar. 24, 1997
Steven P Young, San Jose, CA (US);
Bernard J New, Los Gatos, CA (US);
Nicolas John Camilleri, San Jose, CA (US);
Trevor J Bauer, Campbell, CA (US);
Shekhar Bapat, Santa Clara, CA (US);
Kamal Chaudhary, Milpitas, CA (US);
Sridhar Krishnamurthy, San Jose, CA (US);
XILINX, Inc., San Jose, CA (US);
Abstract
The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. Each tile comprises a logic block that includes a Configurable Logic Element (CLE) and an output multiplexer. Fast feedback paths are provided within the logic block to connect the CLE outputs to the CLE inputs, either directly or through an input multiplexer. The fast feedback paths bypass the output multiplexer and therefore provide faster feedback than can be obtained in most conventional FPGA logic blocks. In one embodiment, the fast feedback paths provide the ability for all function generators in one CLE to drive each other through fast feedback paths, regardless of how logic is mapped into the function generators of the CLE.