The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 22, 2000
Filed:
May. 13, 1999
Applicant:
Inventors:
Steven P Young, San Jose, CA (US);
Bernard J New, Los Gatos, CA (US);
Nicolas John Camilleri, San Jose, CA (US);
Trevor J Bauer, Campbell, CA (US);
Shekhar Bapat, Santa Clara, CA (US);
Kamal Chaudhary, Milpitas, CA (US);
Sridhar Krishnamurthy, San Jose, CA (US);
Assignee:
Xilinx, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
326 41 ; 326 39 ;
Abstract
The invention provides an FPGA comprising an array of identical tiles. Each tile comprises a logic block that includes a Configurable Logic Element (CLE). In one embodiment, the CLE is implemented in two similar portions called 'slices'. Each slice has a separate carry chain. In a CLE with four function generators, each carry chain incorporates the outputs of two function generators.