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Cupertino, CA, United States of America

Narendra V Shenoy

USPTO Granted Patents = 8

Average Co-Inventor Count = 1.9

ph-index = 6

Forward Citations = 109(Granted Patents)

Location History:

Milpitas, CA (US) (1998 - 2002)
Sunnyvale, CA (US) (2002)
Bengaluru, IN (2006 - 2007)
Cupertino, CA (US) (2007 - 2011)

Company Filing History:

Years Active: 1998-2011

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8 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 8042010 - Two-phase clock-stalling technique for error detection and error correction (2011-10-18),

2. 7689957 - Identifying and improving robust designs using statistical timing analysis (2010-03-30),

3. 7260807 - Method and apparatus for designing an integrated circuit using a mask-programmable fabric (2007-08-21),

4. 7260797 - Method and apparatus for estimating parasitic capacitance (2007-08-21),

5. 7100142 - Method and apparatus for creating a mask-programmable architecture from standard cells (2006-08-29),

6. 6397169 - Adaptive cell separation and circuit changes driven by maximum capacitance rules (2002-05-28),

7. 6378114 - Method for the physical placement of an integrated circuit adaptive to netlist changes (2002-04-23),

8. 5822217 - Method and apparatus for improving circuit retiming (1998-10-13),

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