The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 23, 2002
Filed:
Jul. 01, 1997
Narendra V. Shenoy, Sunnyvale, CA (US);
Lukas Van Ginneken, San Jose, CA (US);
Synopsys, Inc., Mountain View, CA (US);
Abstract
In the design of integrated circuits, a computer controlled method for the rough placement of cells. Initially, a synthesis tool is used to generate a netlist according to HDL, user constraint, and technology data. Thereupon, a cell separation process assigns (x,y) locations to each of the cells. The cell location information is supplied to the synthesis tool, which can then make changes to the netlist thereto. In the present invention, the size of the placement area is allowed be scaled according to the new netlist. Next, the cells are spaced apart according to a spacing algorithm. A partitioning algorithm is then applied to group the cells into a plurality of partitions. A number of iterations of cell separation, synthesis of new netlist, size adjustment (if necessary), spacing, and partitioning are performed until the cells converge. Thereupon, detailed placement and routing processes are used to complete the layout.