Synopsys, Inc.

Narendra V Shenoy

Jamil Kawa

Raul Camposano

Mahesh A Iyer

Kevin Michael Harer

Robert F Damiano

Shabbir Husain Batterywala

Florentin Dartu

Lukas Van Ginneken

Hi-Keung Tony Ma

Madhav Desai

One embodiment of the present invention provides a system that augments a circuit design with a mechanism for detecting and correcting timing errors. This system first partitions the circuit into a set of blocks that are clocked by an independent clock source, and integrates an error signal propagation circuit between the set of blocks. For a respective block, the system determines a set of internal registers that are to be implemented as double data sampling registers, and replaces the determined set of internal registers with double data sampling registers, wherein a given double data sampling register is configured to generate an error signal when it detects a timing error. Then, the system integrates a two-phase error correction circuit into the respective block, wherein when notified of a timing error by a double data sampling register, the two-phase error correction circuit is configured to stall registers in the respective block.

Two-phase clock-stalling technique for error detection and error correction

Statistical timing analysis techniques can be used to lead to the construction of robust circuits in a consistent manner through the entire design flow of synthesis, placement and routing. An exemplary technique can include receiving library data for a design including timing models. By comparing implementations of this data, a robust circuit can be defined based on a set of criteria, which can include worst negative slack, endpoint slack distribution, timing constraint violations, and total negative slack. At this point, statistical timing analysis can be used to drive logic changes that generate improved robustness in the design. The statistical timing analysis can use a static timing delay associated with the arc in statistical timing analysis as a mean and a specified percentage of the mean as the standard deviation.

Identifying and improving robust designs using statistical timing analysis

One embodiment of the invention provides a system that facilitates designing an integrated circuit using a mask-programmable fabric, which contains both mask-programmable logic and a mask-programmable interconnect. During operation, the system receives a description of a mask-programmable cell, wherein instances of the mask-programmable cell are repeated to form the mask-programmable fabric. The system uses this description of the mask-programmable cell to generate a derived library containing cells that can be obtained by programming the mask-programmable cell. Next, the system receives a high-level design for the integrated circuit. The system then performs a synthesis operation on the high-level design to generate a preliminary netlist for the high-level design, wherein the preliminary netlist contains references to cells in the derived library. Finally, the system converts the preliminary netlist into a netlist that contains references to the mask-programmable cell with the logic appropriately programmed. The netlist is then placed and routed with the mask programmable constraints on the mask programmable fabric. The design, thus implemented on the programmable fabric, can be changed to accommodate logic revisions and bug fixes by changing only a few masks required for its fabrication.

Method and apparatus for designing an integrated circuit using a mask-programmable fabric

One embodiment of the present invention provides a system for estimating parasitic capacitance for an integrated circuit. During operation, the system reads a technology file, which describes the composition of a vertical cross-section of the integrated circuit. Next, the system reads a design file, which specifies the layout of the integrated circuit. The system then identifies a set of dielectric configurations based on information contained in the technology file. It then computes Green's function for each of these configurations. Next, the system estimates a parasitic capacitance using information contained in the design file and using the set of Green's functions.

Method and apparatus for estimating parasitic capacitance

One embodiment of the invention provides a system for creating a mask-programmable module from standard cells. The system operates by first specifying characteristics of an end design and then selecting a plurality of standard cells from a standard cell library based on the characteristics of the end design. Next, the system combines the plurality of standard cells into a mask-programmable module, wherein instances of the mask-programmable module are repeated to form a mask-programmable fabric. The system also designs a mask-programmable interconnect to match the mask-programmable module, whereby connections within the mask-programmable module and between mask-programmable modules can be generated by programming the mask-programmable interconnect.

Method and apparatus for creating a mask-programmable architecture from standard cells

A process for synthesis and rough placement of an IC design. Initially, a synthesis tool is used to generate a netlist according to HDL, user constraint, and technology data. Each of the wires of the netlist is initially assigned a unit weight. Thereupon, a cell separation process assigns (x,y) locations to each of the cells based on the weights. The wires are then examined to determine their respective performance characteristics. The wires are iteratively re-weighted, and the cells moved according to the new weightings. Next, the cell location information is supplied to the synthesis tool, which can then make changes to the netlist thereto. In the present invention, the size of each of the gates can be either scaled up or down accordingly. Again, the nets are iteratively examined and their weights are adjusted appropriately. The cells are spaced apart according to the new weights.

Adaptive cell separation and circuit changes driven by maximum capacitance rules

In the design of integrated circuits, a computer controlled method for the rough placement of cells. Initially, a synthesis tool is used to generate a netlist according to HDL, user constraint, and technology data. Thereupon, a cell separation process assigns (x,y) locations to each of the cells. The cell location information is supplied to the synthesis tool, which can then make changes to the netlist thereto. In the present invention, the size of the placement area is allowed be scaled according to the new netlist. Next, the cells are spaced apart according to a spacing algorithm. A partitioning algorithm is then applied to group the cells into a plurality of partitions. A number of iterations of cell separation, synthesis of new netlist, size adjustment (if necessary), spacing, and partitioning are performed until the cells converge. Thereupon, detailed placement and routing processes are used to complete the layout.

Method for the physical placement of an integrated circuit adaptive to netlist changes

A method and apparatus for improving the retiming of a circuit. The invention 'tricks' a conventional retiming engine so that the retiming engine will correctly and consistently retime the circuit. Specifically, the present invention adjusts gate delays to account for the fact that registers in the circuit may be moved during retiming. The present invention also includes a methodology for choosing a preferred register from a technology library. Lastly, the present invention also adjusts the clock period of the circuit to account for the fact that the retiming engine assumes a clock-to-state of registers in the circuit to be zero when this is not always the case.

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Cupertino, CA, United States of America

Narendra V Shenoy