Min-Hsiung Chiang

This inventor holds 32 USPTO granted patents, primarily in Integrated Circuit Design. Top assignees: Taiwan Semiconductor Manufacturing Comp. Ltd., Semiconductor Manufacturing Company, Other. Active years: 2000-2018.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Min-Hsiung Chiang. Retrieved from https://idiyas.com/inventor/min-hsiung-chiang

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 32

% Patents Active = 75.0

Average Co-Inventor Count = 2.7

ph-index = 9

Forward Citations = 217(Granted Patents)

Location History:

Pan-Chiao, TW (2000)
Hsin-Chu, TW (2004)
Banciao, TW (2007 - 2008)
Taipei County, TW (2009)
Taipei, TW (2000 - 2017)
New Taipei, TW (2014 - 2018)

Company Filing History:

30 out of 42,810

Taiwan Semiconductor Manufacturing Comp. Ltd.

patents

1 out of 1

Semiconductor Manufacturing Company

patent

1 out of 834,453

Other

patents

Years Active: 2000-2018

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Areas of Expertise:

Integrated Circuits

Semiconductor Structures

Memory Cells

Capacitor Technologies

DRAM Products

Photoresist Layers

Self-Aligned Contacts

MIM Capacitors

Process Simplification

Electrical Failures

Silicon Oxide

CMP Process

32 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 9899263 - Method of forming layout design (2018-02-20),

2. 9691721 - Jog design in integrated circuits (2017-06-27),

3. 9570584 - Semiconductor structure and manufacturing method thereof (2017-02-14),

4. 9355912 - Jog design in integrated circuits (2016-05-31),

5. 9336348 - Method of forming layout design (2016-05-10),

6. 8901627 - Jog design in integrated circuits (2014-12-02),

7. 7622347 - Self-aligned metal electrode to eliminate native oxide effect for metal insulator semiconductor (MIS) capacitor (2009-11-24),

8. 7332394 - Method to reduce a capacitor depletion phenomena (2008-02-19),

9. 7238566 - Method of forming one-transistor memory cell and structure formed thereby (2007-07-03),

10. 7208369 - Dual poly layer and method of manufacture (2007-04-24),

11. 7180116 - Self-aligned metal electrode to eliminate native oxide effect for metal insulator semiconductor (MIS) capacitor (2007-02-20),

12. 6849387 - Method for integrating copper process and MIM capacitor for embedded DRAM (2005-02-01),

13. 6818495 - Method for forming high purity silicon oxide field oxide isolation region (2004-11-16),

14. 6808980 - Method of process simplification and eliminating topography concerns for the creation of advanced 1T-RAM devices (2004-10-26),

15. 6797557 - Methods and systems for forming embedded DRAM for an MIM capacitor (2004-09-28),

Title: Inventor Min-Hsiung Chiang: Revolutionizing Technology from Taipei

Introduction: Min-Hsiung Chiang is a visionary inventor hailing from Taipei, Taiwan, known for his groundbreaking contributions to the field of technology.

Latest Patents: Chiang holds several patents in the areas of artificial intelligence, robotics, and renewable energy, showcasing his innovative spirit and commitment to advancing these fields.

Career Highlights: With a career spanning over two decades, Chiang has worked with leading tech companies, research institutions, and universities to develop cutting-edge technologies that have had a significant impact on various industries.

Collaborations: Throughout his career, Chiang has collaborated with top engineers, scientists, and researchers from around the world, fostering a culture of innovation and excellence in all his projects.

Conclusion: Min-Hsiung Chiang's relentless pursuit of innovation and his passion for pushing the boundaries of technology make him a true pioneer in the field, inspiring the next generation of inventors to dream big and create a better future.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]