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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9899263 B1

PDFFull Text
Date of Patent:
Feb. 20, 2018

Filed:

May. 09, 2016

Method of forming layout design

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Tung-Heng Hsieh, Zhudong Town, TW;

Chung-Te Lin, Tainan, TW;

Sheng-Hsiung Wang, Zhubei, TW;

Hui-Zhong Zhuang, Kaoshung, TW;

Min-Hsiung Chiang, New Taipei, TW;

Ting-Wei Chiang, New Taipei, TW;

Li-Chun Tien, Tainan, TW;

Assignee:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Attorney:

Slater Matsil, LLP

Primary Examiner:

Suchin Parihar

Int. Cl.
CPC ...
G06F 17/50 (2006.01); H01L 21/8234 (2006.01); H01L 27/02 (2006.01); H01L 21/304 (2006.01); H01L 29/66 (2006.01); H01L 21/3213 (2006.01); H01L 27/118 (2006.01);
U.S. Cl.
CPC ...
H01L 21/82345 (2013.01); G06F 17/5072 (2013.01); H01L 21/3043 (2013.01); H01L 21/823431 (2013.01); H01L 27/0207 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 21/32139 (2013.01); H01L 27/11807 (2013.01);
Abstract

A method of forming a layout design for fabricating an integrated circuit (IC) is disclosed. The method includes identifying one or more areas in the layout design occupied by one or more segments of a plurality of gate structure layout patterns of the layout design; and generating a set of layout patterns overlapping the identified one or more areas. The plurality of gate structure layout patterns has a predetermined pitch smaller than a spatial resolution of a predetermined lithographic technology. A first layout pattern of the set of layout patterns has a width less than twice the predetermined pitch.

Find Patent Forward Citations

Hsieh, Tung-Heng. (2018). Method of forming layout design (U.S. Patent No. 9899263). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9899263

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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