The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6797557 B1

PDF
Full Text
Expired
Date of Patent:
Sep. 28, 2004

Filed:

Oct. 11, 2001
Applicant:
Inventor:

Min-Hsiung Chiang, Taipei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/18242 ; H01L 2/144 ;
U.S. Cl.
CPC ...
H01L 2/18242 ; H01L 2/144 ;
Abstract

A method and system for fabricating a capacitor utilized in a semiconductor device. A salicide gate is designated for use with the semiconductor device. A self-aligned contact (SAC) may also be configured for use with the semiconductor device. The salicide gate and the self-aligned contact are generally in a memory cell area of the semiconductor device to thereby permit the efficient shrinkage of memory cell size without an additional mask or weakening of associated circuit performance. Combining, the self-aligned contact and the salicide gate in the same memory cell area can effectively reduce gate resistance.


Find Patent Forward Citations

Chiang, Min-Hsiung. (2004). Methods and systems for forming embedded dram for an mim capacitor (U.S. Patent No. 6797557). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6797557

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…