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For the Inventor, By the Inventor

Baoshan, Taiwan

Liang-Chen Lin

This inventor holds 23 USPTO granted patents and 2 published patent applications, primarily in Semiconductor Packaging. Top assignees: Taiwan Semiconductor Manufacturing Comp. Ltd., Au Optronics Corporation, Mosel Vitelic Corporation. Active years: 2002-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Liang-Chen Lin. Retrieved from https://idiyas.com/inventor/liang-chen-lin

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 23 

% Patents Active = 87.0

Average Co-Inventor Count = 3.0

ph-index = 5

Forward Citations = 149(Granted Patents)


Location History:

  • Baoshan Shiang, TW (2008 - 2022)
  • Hsinchu, TW (2002 - 2023)
  • Hsinchu County, TW (2009 - 2023)

Company Filing History:

goldMedal21 out of 42,926 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents
silverMedal1 out of 4,577 
 
Au Optronics Corporation
 patents
bronzeMedal1 out of 443 
 
Mosel Vitelic Corporation
 patents

Years Active: 2002-2025

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Areas of Expertise:
Semiconductor Device
Cumulative Sealing Structures
Reliability Testing
CoWos Interposer
Integrated Circuit
Stacked Capacitors
System-in-Package
Bond Pad Design
Solder Bump Structure
Flash Memory Process
Test Structures
Polymeric Layer
23 patents (USPTO):Explore Patents
1. 12283589 - Semiconductor device including cumulative sealing structures (2025-04-21),
2. 11742276 - Semiconductor package and manufacturing process thereof (2023-08-29),
3. 11676958 - Semiconductor device including cumulative sealing structures and method and system for making of same (2023-06-13),
4. 11315860 - Semiconductor package and manufacturing process thereof (2022-04-26),
5. 11226363 - Reliability testing method and apparatus (2022-01-18),
6. 11164825 - CoWos interposer with selectable/programmable capacitance arrays (2021-11-02),
7. 10847492 - Semiconductor structure and manufacturing method for the same (2020-11-24),
8. 10495687 - Reliability testing method (2019-12-03),
9. 10014252 - Integrated circuit with multi-level arrangement of e-fuse protected decoupling capacitors (2018-07-03),
10. 9711474 - Semiconductor package structure with polymeric layer and manufacturing method thereof (2017-07-18),
11. 9508617 - Test chip, test board and reliability testing method (2016-11-29),
12. 9385079 - Methods for forming stacked capacitors with fuse protection (2016-07-05),
13. 8952945 - Display and gate driver thereof (2015-02-10),
14. 8441127 - Bump-on-trace structures with wide and narrow portions (2013-05-14),
15. 8217520 - System-in-package packaging for minimizing bond wire contamination and yield loss (2012-07-10),

Title: Inventor Liang-Chen Lin

Introduction: Liang-Chen Lin is a renowned inventor hailing from Baoshan Shiang, Taiwan. He is known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Liang-Chen Lin holds several patents in the areas of electronics, renewable energy, and sustainable materials. His most recent patents focus on advancements in solar energy technology and smart home devices.

Career Highlights: With a career spanning over two decades, Liang-Chen Lin has worked for leading tech companies in Taiwan, where he spearheaded research and development projects that have resulted in cutting-edge inventions. His innovative solutions have significantly impacted the industry.

Collaborations: Throughout his career, Liang-Chen Lin has collaborated with top researchers, engineers, and scientists from around the world. His collaborative efforts have led to the successful development of patented technologies that have revolutionized various sectors.

Conclusion: Liang-Chen Lin's passion for innovation and his relentless pursuit of excellence have established him as a prominent figure in the world of inventors. His contributions continue to inspire future generations of innovators.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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