The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 18, 2017

Filed:

Sep. 24, 2014
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Gia-Her Lu, Hsinchu County, TW;

Liang-Chen Lin, Hsinchu County, TW;

Tung-Chin Yeh, Miaoli County, TW;

Jyun-Lin Wu, Hsinchu, TW;

Tung-Jiun Wu, Hsinchu County, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/683 (2006.01); H01L 23/14 (2006.01); H01L 23/538 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 25/065 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 24/14 (2013.01); H01L 21/6836 (2013.01); H01L 23/147 (2013.01); H01L 23/5384 (2013.01); H01L 24/05 (2013.01); H01L 24/11 (2013.01); H01L 24/17 (2013.01); H01L 24/32 (2013.01); H01L 24/33 (2013.01); H01L 24/73 (2013.01); H01L 24/81 (2013.01); H01L 24/92 (2013.01); H01L 24/94 (2013.01); H01L 24/97 (2013.01); H01L 21/563 (2013.01); H01L 23/3157 (2013.01); H01L 23/3171 (2013.01); H01L 23/49816 (2013.01); H01L 23/5386 (2013.01); H01L 23/562 (2013.01); H01L 24/02 (2013.01); H01L 24/03 (2013.01); H01L 24/06 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/27 (2013.01); H01L 24/29 (2013.01); H01L 24/83 (2013.01); H01L 25/0655 (2013.01); H01L 2221/68327 (2013.01); H01L 2221/68331 (2013.01); H01L 2224/02372 (2013.01); H01L 2224/03002 (2013.01); H01L 2224/036 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04026 (2013.01); H01L 2224/05025 (2013.01); H01L 2224/0569 (2013.01); H01L 2224/05073 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05155 (2013.01); H01L 2224/05557 (2013.01); H01L 2224/05569 (2013.01); H01L 2224/05611 (2013.01); H01L 2224/05644 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05655 (2013.01); H01L 2224/05666 (2013.01); H01L 2224/05681 (2013.01); H01L 2224/05687 (2013.01); H01L 2224/06181 (2013.01); H01L 2224/10126 (2013.01); H01L 2224/11002 (2013.01); H01L 2224/11003 (2013.01); H01L 2224/1131 (2013.01); H01L 2224/1132 (2013.01); H01L 2224/1145 (2013.01); H01L 2224/11334 (2013.01); H01L 2224/11462 (2013.01); H01L 2224/11464 (2013.01); H01L 2224/11849 (2013.01); H01L 2224/131 (2013.01); H01L 2224/133 (2013.01); H01L 2224/13014 (2013.01); H01L 2224/13025 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13116 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13155 (2013.01); H01L 2224/13294 (2013.01); H01L 2224/14131 (2013.01); H01L 2224/14135 (2013.01); H01L 2224/14136 (2013.01); H01L 2224/14177 (2013.01); H01L 2224/14179 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/1703 (2013.01); H01L 2224/17181 (2013.01); H01L 2224/32013 (2013.01); H01L 2224/32058 (2013.01); H01L 2224/32106 (2013.01); H01L 2224/3303 (2013.01); H01L 2224/33181 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81005 (2013.01); H01L 2224/81193 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/83102 (2013.01); H01L 2224/83855 (2013.01); H01L 2224/92 (2013.01); H01L 2224/92125 (2013.01); H01L 2224/92222 (2013.01); H01L 2224/92225 (2013.01); H01L 2224/92242 (2013.01); H01L 2224/94 (2013.01); H01L 2224/97 (2013.01); H01L 2924/00011 (2013.01); H01L 2924/01322 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/18161 (2013.01); H01L 2924/3512 (2013.01);
Abstract

A semiconductor package structure includes a semiconductor substrate including a plurality of through substrate vias (TSV) extending from a first surface to a second surface of the semiconductor substrate, wherein the second surface is opposite to the first surface; a plurality of conductive bumps on the second surface and connected to a corresponding TSV; a polymeric layer on the second surface and surrounding a lower portion of a corresponding conductive bump. The polymeric layer includes a first portion configured as a blanket covering a periphery region of the semiconductor substrate; and a second portion in a core region of the semiconductor substrate and configured as a plurality of isolated belts, wherein each of the isolated belts surrounds a corresponding conductive bump.


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