Taiwan Semiconductor Manufacturing Comp. Ltd.

Au Optronics Corporation

Mosel Vitelic Corporation

Liang-Chen Lin

Pei-Haw Tsao

Pao-Kang Niu

Jyun-Lin Wu

Bill Kiang

Shiang-Ruei Su

I-Tai Liu

Chia-Wei Tu

Shih-Cheng Chang

Fu-Tsai Hou

Tung-Chin Yeh

Gia-Her Lu

Yu-Ting Lin

Hsien-Pin Hu

Li-Huan Chu

Shih-Kai Lin

Hsu-Hsien Chen

Tsung-Yang Hsieh

Ko-Yi Lee

Ta-Chih Peng

Hsin-Hsien Lee

Kuen-Hong Tsai

Kuo-Tung Sung

Tung-Jiun Wu

Thomas Chang

Shih-Chi Lai

Wen-Doe Su

Pi-Chun Yeh

Kuan-Chun Huang

Mao Song Tseng

Chen-Yuan Lei

Kun-Yu Sung

A semiconductor device includes: a core region of core circuitry over a substrate; an input/output (I/O) region of interfacing circuitry over a substrate and coupled to the core region; a sealing ring having first, second and third sides, the sealing ring surrounding, and being isolated from, the core region and the I/O region; an intra-communication (intra-com) stack including intra-com segments in corresponding metallization layers which are stacked, the intra-com segments correspondingly extending between, and thereby coupling, the core region and the I/O region; and a first parapet on the intra-com stack and which extends from the first side to the third side of the sealing ring the first parapet being between, and isolated from each of, the core region and the I/O region.

Semiconductor device including cumulative sealing structures

A package manufacturing process and semiconductor packages are provided. An interposer having a crystal structure is provided. A first die and a second die are bonded on the interposer. The second die is positioned to be spaced apart from the first die with a gap extending direction that is perpendicular to a shortest distance of the gap, and the gap extending direction is not parallel with a crystallographic orientation of the crystal structure of the interposer. A molding compound is formed over the interposer covering the first and second dies. The molding compound and the interposer are cut into packages.

Semiconductor package and manufacturing process thereof

A semiconductor device includes: first and second core regions; first and second input/output (I/O) regions coupled to each other and to the first and second core regions; the first and second I/O regions being between an expendable region and correspondingly the first and second core regions; a sealing ring surrounding the core regions and the I/O regions; metallization layers and interconnection layers; inter-communication (inter-com) segments extending between the I/O regions; first and second parapets which extend from the first to third sides of the sealing ring or from first to second locations on corresponding third and fourth parapets, the latter extending from the first to third sides of the sealing ring; the first parapet being between the first core region and the first I/O region; and the second parapet being between the second core region and the second I/O region.

Semiconductor device including cumulative sealing structures and method and system for making of same

A chip reliability testing method includes mounting a first test chip on a test board, wherein the first test chip comprises a silicon device having a plurality of metallization layers configured to establish a plurality of test circuits, a conductive redistribution layer contacting at least one of the plurality of metallization layers, and contact pads on exposed portions of the conductive redistribution layer. The mounting includes bonding the contact pads of the first test chip to corresponding contact pads of the test board. The method further includes applying a test voltage to a first contact pad connected to a first test circuit of the plurality of test circuits and, while maintaining the test voltage, subjecting the first test circuit to a reliability test. The method further includes monitoring an output voltage at a second contact pad connected to the first test circuit during a test period during the reliability test.

Reliability testing method and apparatus

An interposer circuit includes a substrate and a dielectric layer that is disposed on top of the substrate. The interposer circuit includes two or more connection layers including a first connection layer and a second connection layer that are disposed at different depths in the dielectric layer. The interposer circuit includes a fuse that is disposed in the first connection layer. The first connection layer is coupled to a first power node and the second connection layer is coupled to a first ground node. The interposer circuit further includes a first capacitor that is in series with the fuse and is connected between the first and the second connection layers. The interposer circuit also includes first, second, and third micro-bumps on top of the dielectric layer such that the fuse is coupled between the first and second micro-bumps and the first capacitor is coupled between the second and third micro-bumps.

CoWos interposer with selectable/programmable capacitance arrays

The present disclosure provides a semiconductor structure, including providing a first chip, disposing a first copper layer having a first thickness over a first side of the first chip, and disposing a first solder having a second thickness over the first copper layer, wherein a ratio of the second thickness and the first thickness is in a range of from about 2 to about 3.5.

Semiconductor structure and manufacturing method for the same

Disclosed is a chip reliability testing method that includes mounting a test chip on a test board whereby each test circuit of the test chip is connected to a different pair of input and output terminals. The reliability test can include applying a test voltage to a first (input) bump and measuring an output voltage on a second (output) bump connected to the same test circuit. The first and second bumps are, in turn, electrically connected to each other through a series of conductive materials to define the test circuit. The conductive materials include first and second contact pads under the first and second bumps with the contact pads, in turn, being connected to a conductive substrate or redistribution layer. The conductive substrate or redistribution layer is, in turn, connected to first and second conductive vias that each provide a connection to one or more of a series of conductive layers that are arranged under the conductive substrate or redistribution layer and over a silicon device. A series of dielectric layers are provided between the conductive substrate or redistribution layer, the conductive layers, and the silicon device.

Reliability testing method

An embodiment is a circuit. The circuit includes active circuitry, a first capacitor, a first fuse, a second capacitor, and a second fuse. The active circuitry has a first power node and a second power node. The first capacitor is coupled to the first fuse serially to form a first segment. The second capacitor is coupled to the second fuse serially to form a second segment. The first segment and the second segment are coupled together in parallel and between the first power node and the second power node.

Integrated circuit with multi-level arrangement of e-fuse protected decoupling capacitors

A semiconductor package structure includes a semiconductor substrate including a plurality of through substrate vias (TSV) extending from a first surface to a second surface of the semiconductor substrate, wherein the second surface is opposite to the first surface; a plurality of conductive bumps on the second surface and connected to a corresponding TSV; a polymeric layer on the second surface and surrounding a lower portion of a corresponding conductive bump. The polymeric layer includes a first portion configured as a blanket covering a periphery region of the semiconductor substrate; and a second portion in a core region of the semiconductor substrate and configured as a plurality of isolated belts, wherein each of the isolated belts surrounds a corresponding conductive bump.

Semiconductor package structure with polymeric layer and manufacturing method thereof

A test board includes a first chip mounting area, a first input area, a second input area, a first output area, and a second output area. The test board also includes a first conductive pattern, a second conductive pattern, a third conductive pattern, and a fourth conductive pattern. The first conductive pattern electrically connects a first pin of the first input area and a first pin of the first chip mounting area. The second conductive pattern electrically connects a first pin of the second input area and a second pin of the first chip mounting area. The third conductive pattern electrically connects a first pin of the first output area and a third pin of the first chip mounting area. The fourth conductive pattern electrically connects a first pin of the second output area and a fourth pin of the first chip mounting area.

Test chip, test board and reliability testing method

Methods for forming stacked capacitors with fuse protection

A display and a gate driver are disclosed herein, in which the gate driver includes a number of gate driving units, and each of the gate driving units includes a control circuit, a boost circuit, a driver output circuit and a voltage stabilized circuit. The control circuit is electrically connected to a previous gate driving unit and a next gate driving unit. The boost circuit is electrically connected to the control circuit for driving the next gate driving unit. The driver output circuit is electrically connected to the boost circuit and a pixel array for driving at least one scan line in the pixel array. The voltage stabilizing circuit is electrically connected to the boost circuit and the driver output circuit.

Display and gate driver thereof

A device includes a package component, and a metal trace on a surface of the package component. A first and a second dielectric mask cover a top surface and sidewalls of the metal trace, wherein a landing portion of the metal trace is located between the first and the second dielectric masks. The landing portion includes a first portion having a first width, and a second portion connected to an end of the first portion. The second portion has a second width greater than the first width, wherein the first and the second widths are measured in a direction perpendicular to a lengthwise direction of the metal trace.

Bump-on-trace structures with wide and narrow portions

A system-in-package (SiP) package is provided. In one embodiment, the SiP package comprises a substrate having a first surface and a second surface opposite the first surface, the substrate having a set of bond wire studs on bond pads formed on the second surface thereof; a first semiconductor chip having a first surface and a second surface opposite the first surface, wherein the first surface of the first semiconductor chip is mounted to the second surface of the substrate by means of solder bumps; an underfill material disposed between the first semiconductor chip and the substrate, encapsulating the solder bumps; a second semiconductor chip having a first surface and a second surface opposite the first surface, wherein the first surface of the second semiconductor chip is mounted to the second surface of the first semiconductor chip; and a set of bond wires electrically coupled from the second semiconductor chip to the set of bond wire studs on the substrate.

Growing community of inventors

Baoshan Shiang, Taiwan

Liang-Chen Lin