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For the Inventor, By the Inventor

Tokyo, Japan

Kazuo Nakaizumi

This inventor holds 18 USPTO granted patents, primarily in Semiconductor Circuits. Top assignees: Nec Corporation, Ando Electric Company, Nippon Electric Co., Ltd.. Active years: 1986-2002.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kazuo Nakaizumi. Retrieved from https://idiyas.com/inventor/kazuo-nakaizumi

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 18

% Patents Active = 88.9

Average Co-Inventor Count = 1.2

ph-index = 11

Forward Citations = 318(Granted Patents)


Company Filing History:

goldMedal12 out of 36,718 
 
Nec Corporation
 patents
silverMedal4 out of 389 
 
Ando Electric Company
 patents
bronzeMedal2 out of 1,038 
 
Nippon Electric Co., Ltd.
 patents

Years Active: 1986-2002

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Areas of Expertise:
D-FF Circuit
Temperature Stabilizing Circuit
Memory Circuit
Testing Semiconductor Wafer
Integrated Circuits
Redundant Memory Cell
High Speed Latching Circuit
Static Memory Device
Dynamic Memory Device
Charging Current
Digital Circuit
Signal Input Circuit
18 patents (USPTO):Explore Patents
1. 6459302 - D-FF circuit (2002-10-01),
2. 6429713 - D-FF circuit (2002-08-06),
3. 6388473 - Logic product circuit (2002-05-14),
4. 6249173 - Temperature stabilizing circuit (2001-06-19),
5. 6133744 - Apparatus for testing semiconductor wafer (2000-10-17),
6. 6031382 - Functional tester for integrated circuits (2000-02-29),
7. 5532610 - Apparatus for testing semicondctor wafer (1996-07-02),
8. 5058059 - Memory circuit having a redundant memory cell array for replacing faulty (1991-10-15),
9. 4985866 - Compound semiconductor memory device having redundant circuit (1991-01-15),
10. 4982111 - High speed latching circuit with level shift output circuits (1991-01-01),
11. 4933903 - Static memory device provided with high-speed writing circuit (1990-06-12),
12. 4878201 - Semiconductor memory device having an improved timing signal generator (1989-10-31),
13. 4825415 - Signal input circuit having signal latch function (1989-04-25),
14. 4688196 - Semiconductor dynamic memory device with less power consumption in (1987-08-18),
15. 4672583 - Dynamic random access memory device provided with test circuit for (1987-06-09),

Title: Kazuo Nakaizumi: Innovator in Circuit Design

Introduction

Kazuo Nakaizumi is a prominent inventor based in Tokyo, Japan. He has made significant contributions to the field of circuit design, holding a total of 18 patents. His innovative work has paved the way for advancements in electronic circuits, particularly in flip-flop technology.

Latest Patents

Among his latest inventions is the D-FF circuit, which comprises a master flip-flop and a slave flip-flop that operate in accordance with multiple clock signals generated by a clock signal generating circuit. The slave flip-flop features a clocked inverter on its first stage, which operates based on at least one of the clock signals. Additionally, he has developed another D-FF circuit that allows the master and slave flip-flops to operate at predetermined timings, enhancing the efficiency of circuit operations.

Career Highlights

Kazuo Nakaizumi has worked with notable companies such as NEC Corporation and Ando Electric Company. His experience in these organizations has contributed to his expertise in circuit design and innovation.

Collaborations

He has collaborated with esteemed colleagues, including Tohru Tsujide and Yasaburo Inagaki, further enriching his work and contributions to the field.

Conclusion

Kazuo Nakaizumi's innovative spirit and dedication to circuit design have led to significant advancements in technology. His contributions continue to influence the industry and inspire future inventors.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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