The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6429713 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 06, 2002

Filed:

Feb. 23, 2001
Applicant:
Inventor:

Kazuo Nakaizumi, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/289 ; H03K 3/12 ;
U.S. Cl.
CPC ...
H03K 3/289 ; H03K 3/12 ;
Abstract

A D-FF circuit for operating a master flip-flop and a slave flip-flop at each predetermined timing in accordance with a plurality of clock signals generated by a clock signal generating circuit, wherein the clock signal generating circuit generates the plurality of clock signals at different timings, the slave flip-flop starts operating in accordance with a clock signal which is generated at an earlier timing than another clock signal generated by the clock signal generating circuit, and the master flip-flop stops operating in accordance with a clock signal which is generated at a later timing than another clock signal generated by the clock signal generating circuit.


Find Patent Forward Citations

Nakaizumi, Kazuo. (2002). D-ff circuit (U.S. Patent No. 6429713). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6429713

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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