The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 01, 2002
Filed:
Mar. 27, 2001
Applicant:
Inventor:
Kazuo Nakaizumi, Tokyo, JP;
Assignee:
Ando Electric Co., Ltd., Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 1/900 ;
U.S. Cl.
CPC ...
H03K 1/900 ;
Abstract
A D-FF circuit comprises: a master flip-flop and a slave flip-flop which operate in accordance with a plurality of clock signals generated by a clock signal generating circuit; wherein the slave flip-flop comprises: a clocked inverter which is disposed on a first stage of the slave flip-flop and which operates in accordance with at least one of the plurality of clock signals generated by the clock signal generating circuit, and a two-stage inverter which is connected in series with an output terminal of the clocked inverter.
Nakaizumi, Kazuo. (2002). D-ff circuit (U.S. Patent No. 6459302). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6459302
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile