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For the Inventor, By the Inventor

Yonghe, Taiwan

Kang-Cheng Lin

This inventor holds 17 USPTO granted patents. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2004-2016.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kang-Cheng Lin. Retrieved from https://idiyas.com/inventor/kang-cheng-lin

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 17

% Patents Active = 64.7

Average Co-Inventor Count = 3.3

ph-index = 6

Forward Citations = 141(Granted Patents)


Location History:

  • Yunghe, TW (2004 - 2007)
  • Taipei, TW (2010)
  • Yonghe, TW (2009 - 2014)
  • Hsin-Chu, TW (2005 - 2016)

Company Filing History:

goldMedal17 out of 42,810 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents

Years Active: 2004-2016

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17 patents (USPTO):Explore Patents
1. 9263445 - Method of fabricating dual high-k metal gates for MOS devices (2016-02-16),
2. 8853068 - Method of fabricating dual high-k metal gate for MOS devices (2014-10-07),
3. 8836038 - CMOS dual metal gate semiconductor device (2014-09-16),
4. 8541264 - Method for forming semiconductor structure having protection layer for preventing laser damage (2013-09-24),
5. 8450161 - Method of fabricating a sealing structure for high-k metal gate (2013-05-28),
6. 8242576 - Protection layer for preventing laser damage on semiconductor devices (2012-08-14),
7. 8193586 - Sealing structure for high-K metal gate (2012-06-05),
8. 8159035 - Metal gates of PMOS devices having high work functions (2012-04-17),
9. 8105931 - Method of fabricating dual high-k metal gates for MOS devices (2012-01-31),
10. 7829949 - High-K dielectric metal gate device structure (2010-11-09),
11. 7812414 - Hybrid process for forming metal gates (2010-10-12),
12. 7667289 - Fuse structure having a tortuous metal fuse line (2010-02-23),
13. 7625791 - High-k dielectric metal gate device structure and method for forming the same (2009-12-01),
14. 7312486 - Stripe board dummy metal for reducing coupling capacitance (2007-12-25),
15. 6960496 - Method of damascene process flow (2005-11-01),

Title: Kang-Cheng Lin: Innovator in Semiconductor Technology

Introduction

Kang-Cheng Lin is a prominent inventor based in Yonghe, Taiwan. He has made significant contributions to the field of semiconductor technology, holding a total of 17 patents. His work focuses on innovative methods for fabricating advanced semiconductor devices.

Latest Patents

Among his latest patents is a method of fabricating dual high-k metal gates for MOS devices. This patent outlines a comprehensive process that includes providing a semiconductor substrate with distinct regions, forming a high-k dielectric layer, and creating gate stacks that enhance device performance. The method emphasizes the protection of metal layers during treatment processes, showcasing Lin's expertise in semiconductor fabrication.

Career Highlights

Kang-Cheng Lin is currently employed at Taiwan Semiconductor Manufacturing Company Ltd., a leading firm in the semiconductor industry. His role involves developing cutting-edge technologies that push the boundaries of semiconductor manufacturing. His innovative approaches have positioned him as a key player in the field.

Collaborations

Lin has collaborated with notable colleagues, including Kuo-Tai Huang and Peng-Fu Hsu. These partnerships have fostered a collaborative environment that enhances the development of new technologies in semiconductor fabrication.

Conclusion

Kang-Cheng Lin's contributions to semiconductor technology through his patents and collaborations highlight his role as an influential inventor in the industry. His innovative methods continue to shape the future of semiconductor devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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