The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 28, 2013
Filed:
May. 07, 2012
Chien-hao Chen, Chungwei Township, Ilan County, TW;
Hao-ming Lien, Hsinchu, TW;
Ssu-yu LI, Hsinchu, TW;
Jun-lin Yeh, Hsinchu, TW;
Kang-cheng Lin, Yonghe, TW;
Kuo-tai Huang, Hsinchu, TW;
Chii-horng LI, Jhu-Bei, TW;
Chien-liang Chen, Hsinchu, TW;
Chung-hau Fei, Hsinchu, TW;
Wen-chih Yang, Changhua, TW;
Jin-aun NG, Hsinchu, TW;
Chi Hsin Chang, Banciao, TW;
Chun Ming Lin, Hsinchu, TW;
Harry Chuang, Hsinchu, TW;
Chien-Hao Chen, Chungwei Township, Ilan County, TW;
Hao-Ming Lien, Hsinchu, TW;
Ssu-Yu Li, Hsinchu, TW;
Jun-Lin Yeh, Hsinchu, TW;
Kang-Cheng Lin, Yonghe, TW;
Kuo-Tai Huang, Hsinchu, TW;
Chii-Horng Li, Jhu-Bei, TW;
Chien-Liang Chen, Hsinchu, TW;
Chung-Hau Fei, Hsinchu, TW;
Wen-Chih Yang, Changhua, TW;
Jin-Aun Ng, Hsinchu, TW;
Chi Hsin Chang, Banciao, TW;
Chun Ming Lin, Hsinchu, TW;
Harry Chuang, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.