The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 25, 2007
Filed:
Jul. 05, 2002
Kang-cheng Lin, Yunghe, TW;
Chin-chiu Hsia, Taipei, TW;
Kang-Cheng Lin, Yunghe, TW;
Chin-Chiu Hsia, Taipei, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
Dishing is known to be a problem after CMP of dielectric layers in which the distribution of embedded metal is non-uniform. This problem has been solved by populating those areas where the density of embedded metal is low with unconnected regions that, instead of being uniformly filled with metal, are made up of metallic patterns whose combined area within a given region is about half the total area of the region itself. Two examples of such patterns are a line stripe pattern (similar to a parquet flooring tile) and a checker board pattern. Data is presented comparing the parasitic capacitances resulting from the use of patterns of this type relative to conventional solid patterns. The effect of aligning the regions so as to reduce their degree of overlap with wiring channels is also discussed.