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For the Inventor, By the Inventor

Tucheng, Taiwan

Jyh-Rong Lin

This inventor holds 15 USPTO granted patents. Top assignees: Industrial Technology Research Institute, Adeia Semiconductor Bonding Technologies Inc., Hong Kong Applied Science and Technology Research Institute. Active years: 2001-2017.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jyh-Rong Lin. Retrieved from https://idiyas.com/inventor/jyh-rong-lin

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 15

% Patents Active = 66.7

Average Co-Inventor Count = 5.0

ph-index = 8

Forward Citations = 322(Granted Patents)


Location History:

  • Taipei, TW (2001 - 2012)
  • Tu-Cheng, TW (2003 - 2017)

Company Filing History:

goldMedal9 out of 9,307 
 
Industrial Technology Research Institute
 patents
silverMedal4 out of 1,909 
 
Adeia Semiconductor Bonding Technologies Inc.
 patents
bronzeMedal2 out of 611 
 
Hong Kong Applied Science and Technology Research Institute
 patents

Years Active: 2001-2017

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15 patents (USPTO):Explore Patents
1. 9601474 - Electrically stackable semiconductor wafer and chip packages (2017-03-21),
2. 9059181 - Wafer leveled chip packaging structure and method thereof (2015-06-16),
3. 8587091 - Wafer-leveled chip packaging structure and method thereof (2013-11-19),
4. 8314482 - Semiconductor package device (2012-11-20),
5. 8248803 - Semiconductor package and method of manufacturing the same (2012-08-21),
6. 7879438 - Substrate warpage-reducing structure (2011-02-01),
7. 7838333 - Electronic device package and method of manufacturing the same (2010-11-23),
8. 7632707 - Electronic device package and method of manufacturing the same (2009-12-15),
9. 7572676 - Packaging structure and method of an image sensor module (2009-08-11),
10. 7528009 - Wafer-leveled chip packaging structure and method thereof (2009-05-05),
11. 7411306 - Packaging structure and method of an image sensor module (2008-08-12),
12. 7294920 - Wafer-leveled chip packaging structure and method thereof (2007-11-13),
13. 6605525 - Method for forming a wafer level package incorporating a multiplicity of elastomeric blocks and package formed (2003-08-12),
14. 6358836 - Wafer level package incorporating elastomeric pads in dummy plugs (2002-03-19),
15. 6277669 - Wafer level packaging method and packages formed (2001-08-21),

Title: Inventor Jyh-Rong Lin

Introduction: Jyh-Rong Lin is a renowned inventor hailing from Tucheng, Taiwan, known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Jyh-Rong Lin holds several patents in the areas of electronics, semiconductor devices, and renewable energy technologies, showcasing his versatility and expertise in various domains.

Career Highlights: With a career spanning over two decades, Jyh-Rong Lin has worked with leading tech companies and research institutions, playing a pivotal role in developing cutting-edge solutions that have revolutionized the industry.

Collaborations: Throughout his career, Jyh-Rong Lin has collaborated with top researchers, engineers, and scientists, fostering a culture of innovation and knowledge sharing that has led to numerous successful projects and inventions.

Conclusion: Jyh-Rong Lin's passion for innovation, coupled with his technical acumen, has established him as a key figure in the world of technology, inspiring future generations of inventors and pushing the boundaries of what is possible in the realm of inventions.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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