The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 13, 2007
Filed:
Jul. 22, 2005
Shou-lung Chen, Yangmei Township, Taoyuan County, TW;
Ching-wen Hsiao, Banciao, TW;
Yu-hua Chen, Mingjian Shiang, TW;
Jeng-dar Ko, Pade, TW;
Chih-ming Tzeng, Fengshan, TW;
Jyh-rong Lin, Tucheng, TW;
Shan-pu Yu, Chiayi, TW;
Shou-Lung Chen, Yangmei Township, Taoyuan County, TW;
Ching-Wen Hsiao, Banciao, TW;
Yu-Hua Chen, Mingjian Shiang, TW;
Jeng-Dar Ko, Pade, TW;
Chih-Ming Tzeng, Fengshan, TW;
Jyh-Rong Lin, Tucheng, TW;
Shan-Pu Yu, Chiayi, TW;
Industrial Technology Research Institute, Hsinchu, TW;
Abstract
This invention relates to a wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.