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Dadu, Taiwan

Jung-Ching Chen

This inventor holds 14 USPTO granted patents. Top assignee: United Microelectronics Corp.. Active years: 2006-2015.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jung-Ching Chen. Retrieved from https://idiyas.com/inventor/jung-ching-chen

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 14

% Patents Active = 100.0

Average Co-Inventor Count = 2.9

ph-index = 5

Forward Citations = 88(Granted Patents)


Location History:

  • Tai-Chung Hsien, TW (2006 - 2009)
  • Dadu Township, Taichung County, TW (2007 - 2011)
  • Hsinchu, TW (2009 - 2011)
  • Taichung, TW (2015)

Company Filing History:

goldMedal14 out of 7,278 
 
United Microelectronics Corp.
 patents

Years Active: 2006-2015

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14 patents (USPTO):Explore Patents
1. 9153454 - Method of fabricating high voltage device (2015-10-06),
2. 8026549 - LDMOS with N-type isolation ring and method of fabricating the same (2011-09-27),
3. 7868372 - Depletion-mode single-poly EEPROM cell (2011-01-11),
4. 7741659 - Semiconductor device (2010-06-22),
5. 7528076 - Method for manufacturing gate oxide layer with different thicknesses (2009-05-05),
6. 7479426 - Method of manufacturing non-volatile memory cell (2009-01-20),
7. 7408221 - Electrically erasable programmable read-only memory cell and memory device and manufacturing method thereof (2008-08-05),
8. 7405442 - Electrically erasable programmable read-only memory cell and memory device (2008-07-29),
9. 7405123 - Electrically erasable programmable read-only memory cell and memory device and manufacturing method thereof (2008-07-29),
10. 7388250 - Non-volatile memory cell and manufacturing method thereof (2008-06-17),
11. 7256092 - Method for fabricating integrated circuits having both high voltage and low voltage devices (2007-08-14),
12. 7250339 - Electrically erasable programmable read-only memory cell and memory device and manufacturing method thereof (2007-07-31),
13. 7244975 - High-voltage device structure (2007-07-17),
14. 7091079 - Method of forming devices having three different operation voltages (2006-08-15),

Title: Innovations of Jung-Ching Chen

Introduction

Jung-Ching Chen is a prominent inventor based in Dadu, Taiwan. He has made significant contributions to the field of semiconductor technology, holding a total of 14 patents. His work focuses on advanced methods for fabricating high voltage devices and semiconductor components.

Latest Patents

One of his latest patents is a method of fabricating a high voltage device. This method includes the step of forming a patterned photoresist layer on a conductive layer and a dielectric layer below the conductive layer. The conductive layer and the dielectric layer are then patterned by using the patterned photoresist layer as a mask. Following this, the patterned photoresist layer is shrunk, allowing for further patterning of the conductive and dielectric layers. Another notable patent is for an LDMOS with an N-type isolation ring and the method of fabricating the same. This invention describes a semiconductor device and an integrated circuit chip, featuring a deep N-well region configured in a substrate, surrounded by a P-well region. The gate structure is placed on the substrate of the deep N-well region, with various doped regions and isolation structures enhancing the device's performance.

Career Highlights

Jung-Ching Chen is currently employed at United Microelectronics Corporation, a leading company in the semiconductor industry. His expertise and innovative approaches have positioned him as a key figure in the development of advanced semiconductor technologies.

Collaborations

Throughout his career, Jung-Ching Chen has collaborated with notable colleagues, including Chuang-Hsin Chueh and Spring Chen. These collaborations have further enriched his work and contributed to the advancement of semiconductor innovations.

Conclusion

Jung-Ching Chen's contributions to semiconductor technology through his patents and collaborations highlight his role as a significant inventor in the field. His innovative methods continue to influence the industry and pave the way for future advancements.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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